Method for efficiently calculating syndromes in reed-solomon decoding, and machine-readable storage medium storing instructions for executing the method
First Claim
1. A method for efficiently calculating syndromes in Reed-Solomon coding, which is adapted to be implemented in a processor having a parallel processing instruction set, the method comprising the following steps:
- (a) initializing a syndrome vector;
(b) obtaining a symbol from a Reed-Solomon block code;
(c) finding a lookup index based on the symbol;
(d) using the parallel processing instruction set, obtaining a finite field product vector corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector;
(e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and
(f) outputting the updated syndrome vector.
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Abstract
A method for efficiently calculating syndromes in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes: (a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector Corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector.
8 Citations
10 Claims
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1. A method for efficiently calculating syndromes in Reed-Solomon coding, which is adapted to be implemented in a processor having a parallel processing instruction set, the method comprising the following steps:
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(a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector. - View Dependent Claims (3, 4, 5)
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2. The method according to claim , further comprising, between steps (e) and (f), a step (g) of repeating steps (b) to (e).
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6. A machine-readable recording medium, which stores a plurality of instructions, the instructions being used to execute the following steps in a processor having a parallel processing instruction set:
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(a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector. - View Dependent Claims (7, 8, 9, 10)
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Specification
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- Resources
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Current AssigneeLite-On Technology Corporation
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Original AssigneeLite-On Technology Corporation
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InventorsHsu, Matthew
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current714/759
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CPC Class CodesH03M 13/1515 Reed-Solomon codesH03M 13/157 Polynomial evaluation, i.e....H03M 13/6561 Parallelized implementationsH03M 13/6569 Implementation on processor...
