Manufacturing Aware Design and Design Aware Manufacturing

• US 20080307371A1
• Filed: 06/09/2008
• Published: 12/11/2008
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Akira Fujimura, Louis K. Scheffer
• Original Assignee: Akira Fujimura, Louis K. Scheffer
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Granted Patent: US 8,020,135 B2
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091

Abstract

Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout.

Claims

1-15. -15. (canceled)

16. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

a. specifying an illumination configuration;

b. defining a wiring configuration based on the specified illumination configuration; and

c. using the defined wiring configuration to route the IC layout.

17. The process of claim 16, wherein specifying the illumination configuration comprises specifying a dipole lens for a first layer of the IC layout.

18. The process of claim 17, wherein defining the wiring configuration comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

19. The process of claim 18, wherein the dipole lens comprises two poles that are vertically aligned, wherein the first direction is a horizontal direction.

20. The process of claim 18, wherein the dipole lens comprises two poles that are horizontally aligned, wherein the first direction is a vertical direction.

21. The process of claim 18, wherein the dipole lens comprises two poles that are 45°

diagonally aligned, wherein the first direction is a 135°

diagonal direction.

22. The process of claim 18, wherein the dipole lens comprises two poles that are 135°

diagonal aligned, wherein the first direction is a 45°

diagonal direction.

23. The process of claim 16, wherein specifying illumination configuration comprises specifying a first dipole lens and a second dipole lens for a first layer for the IC layout.

24. The process of claim 23, wherein defining the wiring configuration comprises defining a narrow route in a first direction of the first layer and a narrow route in a second direction of the first layer.

25. The process of claim 24, wherein the first dipole lens comprises two poles that are vertically aligned, wherein the second dipole lens comprises two poles that are horizontally aligned.

26. The process of claim 25, wherein the first direction is a horizontal direction, wherein the second direction is a vertical direction.

27. The process of claim 24, wherein the first dipole lens comprises two poles that are 45°

diagonally aligned, wherein the second dipole lens comprises two poles that are 135°

diagonally aligned.

28. The process of claim 27, wherein the first direction is a 135°

diagonal direction, wherein the second direction is a 45°

diagonal direction.

29. The process of claim 16, wherein specifying the illumination configuration comprises specifying a quadrupole lens for a first layer of the IC layout.

30. The process of claim 29, wherein defining the wiring configuration comprises defining a narrow route in a first direction of the first layer and a narrow route in a second direction of the first layer.

31. The process of claim 30, wherein the quadrupole lens comprises four poles, wherein the first and second poles are vertically aligned, wherein the third and fourth poles are horizontally aligned.

32. The process of claim 31, wherein the first direction is a horizontal direction, wherein the second direction is a vertical direction.

33. The process of claim 30, wherein the quadrupole lens comprises four poles, wherein the first and second poles are 45°

diagonally aligned, wherein the third and fourth poles are 135°

diagonally aligned.

34. The process of claim 33, wherein the first direction is a 135°

diagonal direction, wherein the second direction is a 45°

diagonal direction.

35. The process of claim 16, wherein specifying an illumination configuration comprises specifying a stepper lens for each layer of the IC layout.

36. The process of claim 35, wherein defining a wiring configuration based on the specified illumination configuration comprises defining a first width for a first route for each layer of the IC layout based on the corresponding specified stepper lens.

37. The process of claim 16 wherein the illumination configuration comprises at least one of off-axis illumination and on-axis illumination.

38. The process of claim 19, wherein the poles of the dipole lens comprise at least one of a circular shape, a non-circular shape and an elliptical shape.

39. The process of claim 16, wherein specifying the illumination configuration comprises specifying at least one of an octagonal lens for a first layer of the IC layout and an annular lens for the first layer of the IC layout.

40. A manufacturing aware process for designing an integrated circuit (“

IC”

), the process comprising;

a. concurrently identifying (i) based on a fabrication technology, an illumination configuration to be used in manufacturing the IC and (ii) based on a wiring model, dimensional attributes of a plurality of routes for use in an IC layout;

b. after the concurrent identification of the illumination configuration and dimensional attributes, utilizing software tools to design the IC layout; and

c. using the identified illumination configuration to manufacture the IC based on the identified dimensional attributes of the plurality of routes.