Thin film transistor array panel and manufacturing method thereof
First Claim
1. A thin film transistor array panel comprising:
- an insulating substrate;
a channel layer including an oxide material formed on the insulating substrate;
a gate insulating layer formed on the channel layer;
a gate electrode formed on the gate insulating layer;
an interlayer insulating layer formed on the gate electrode;
a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer;
a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer;
a pixel electrode comprising a portion of the first conductive layer associated with the drain electrode;
a passivation layer formed on the data line and the drain electrode; and
a spacer formed on the passivation layer.
2 Assignments
0 Petitions
Accused Products
Abstract
The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
-
Citations
25 Claims
-
1. A thin film transistor array panel comprising:
-
an insulating substrate; a channel layer including an oxide material formed on the insulating substrate; a gate insulating layer formed on the channel layer; a gate electrode formed on the gate insulating layer; an interlayer insulating layer formed on the gate electrode; a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer; a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer; a pixel electrode comprising a portion of the first conductive layer associated with the drain electrode; a passivation layer formed on the data line and the drain electrode; and a spacer formed on the passivation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A thin fil transistor array panel comprising:
-
an insulating substrate; a channel layer including an oxide material formed on the insulating substrate; a gate insulating layer formed on the channel layer; a gate line formed on the gate insulating layer; an interlayer insulating layer formed on the gate line; a data line including a source electrode and a drain electrode formed on the interlayer insulating layer; a pixel electrode formed on the interlayer insulating layer, and connected to the drain electrode; a passivation layer formed on the data line and the drain electrode; and a spacer formed on the passivation layer, wherein the passivation layer is coextensive with the data line, and further wherein the passivation layer includes a portion covering the drain electrode. - View Dependent Claims (16, 17)
-
-
18. A method for manufacturing a thin film transistor array panel comprising:
-
forming a channel layer including an oxide on an insulating substrate; forming a gate insulating layer covering the channel layer; forming a gate line including a gate electrode on the gate insulating layer; forming an interlayer insulating layer on the gate line; forming a plurality of contact holes in the interlayer insulating layer exposing portions of the channel layer and the gate insulating layer; forming a data line including a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode on the interlayer insulating layer; forming an insulating layer on the data line, drain electrode, and pixel electrode; forming a spacer on the insulating layer; and etching the insulating layer using the spacer as an etching mask to form a passivation layer exposing the pixel electrode. - View Dependent Claims (19, 20, 21, 22, 23, 24)
-
-
25. A method for manufacturing a thin film transistor array panel comprising:
-
forming a channel layer including an oxide on an insulating substrate; forming a gate insulating layer covering the channel layer; forming a gate line including a gate electrode on the gate insulating layer; forming an interlayer insulating layer on the gate line; forming a plurality of contact holes exposing portions of the channel layer in the interlayer insulating layer and the gate insulating layer; sequentially depositing a first conductive layer and a second conductive layer on the interlayer insulating layer; forming a first photosensitive film pattern having a different thickness according to position on the second conductive layer; etching the second conductive layer and the first conductive layer using the first photosensitive film pattern as an etching mask to form a data line including a source electrode, a drain electrode, and a previous pixel electrode connected to the drain electrode; ashing the first photosensitive film pattern to form a second photosensitive film pattern exposing the second conductive layer of the previous pixel electrode; etching the second conductive layer using the second photosensitive film pattern as an etching mask to form a pixel electrode; forming a passivation layer on the data line, the drain electrode, and the pixel electrode; and forming a spacer on the passivation layer.
-
Specification