Thin film transistor array panel and manufacturing method thereof

• US 20080308795A1
• Filed: 10/30/2007
• Published: 12/18/2008
• Est. Priority Date: 06/14/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Je-Hun, Jeong, Chang-Oh, Kim, Do-Hyun
• Granted Patent: US 7,863,607 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a channel layer including an oxide material formed on the insulating substrate;

a gate insulating layer formed on the channel layer;

a gate electrode formed on the gate insulating layer;

an interlayer insulating layer formed on the gate electrode;

a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer;

a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer;

a pixel electrode comprising a portion of the first conductive layer associated with the drain electrode;

a passivation layer formed on the data line and the drain electrode; and

a spacer formed on the passivation layer.

2. The thin film transistor array panel of claim 1, wherein

the passivation layer extends above the data line, and includes a protruded portion covering the drain electrode.

3. The thin film transistor array panel of claim 2, wherein

the spacer has the same planar shape as the passivation layer.

4. The thin film transistor array panel of claim 2, wherein

the spacer covers less than all of the passivation layer

5. The thin film transistor array panel of claim 4, wherein

the gate insulating layer has substantially the same planar shape as the channel layer.

6. The thin film transistor array panel of claim 1, further comprising:

a storage electrode line formed on a portion of the substrate, except on the gate insulating layer, and intersecting the data line.

7. The thin film transistor array panel of claim 1, further comprising:

a color filter formed on the pixel electrode.

8. The thin film transistor array panel of claim 1, further comprising:

a color filter formed between the interlayer insulating layer and the pixel electrode.

9. The thin film transistor array panel of claim 1, further comprising:

a color filter formed between the substrate and the channel layer.

10. The thin film transistor array panel of claim 1, wherein the gate insulating layer has substantially the same planar shape as the channel layer

11. The thin film transistor array panel of claim 10, further comprising:

a storage electrode line formed on the substrate.

12. The thin film transistor array panel of claim 10, further comprising:

a color filter formed on the pixel electrode.

13. The thin film transistor array panel of claim 10, further comprising:

a color filter formed between the interlayer insulating layer and the pixel electrode.

14. The thin film transistor array panel of claim 10, further comprising:

a color filter formed between the substrate and the channel layer.

15. A thin fil transistor array panel comprising:

an insulating substrate;

a channel layer including an oxide material formed on the insulating substrate;

a gate insulating layer formed on the channel layer;

a gate line formed on the gate insulating layer;

an interlayer insulating layer formed on the gate line;

a data line including a source electrode and a drain electrode formed on the interlayer insulating layer;

a pixel electrode formed on the interlayer insulating layer, and connected to the drain electrode;

a passivation layer formed on the data line and the drain electrode; and

a spacer formed on the passivation layer,

wherein the passivation layer is coextensive with the data line, and further wherein the passivation layer includes a portion covering the drain electrode.

16. The thin film transistor array panel of claim 15, wherein

the spacer has the substantially same planar shape as the passivation layer.

17. The thin film transistor array panel of claim 15, wherein

the spacer covers less than all of the passivation layer.

18. A method for manufacturing a thin film transistor array panel comprising:

forming a channel layer including an oxide on an insulating substrate;

forming a gate insulating layer covering the channel layer;

forming a gate line including a gate electrode on the gate insulating layer;

forming an interlayer insulating layer on the gate line;

forming a plurality of contact holes in the interlayer insulating layer exposing portions of the channel layer and the gate insulating layer;

forming a data line including a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode on the interlayer insulating layer;

forming an insulating layer on the data line, drain electrode, and pixel electrode;

forming a spacer on the insulating layer; and

etching the insulating layer using the spacer as an etching mask to form a passivation layer exposing the pixel electrode.

19. The method of claim 18, wherein

the forming of the data line, the drain electrode, and the pixel electrode on the interlayer insulating layer includes:

sequentially depositing a first conductive layer and the second conductive layer;

forming a first photosensitive film pattern having different thickness according to position on the second conductive layer;

etching the second conductive layer and the first conductive layer using the first photosensitive film pattern as an etching mask;

ashing the first photosensitive film pattern to form a second photosensitive film pattern exposing the second conductive layer; and

etching the second conductive layer using the second photosensitive film pattern as an etching mask.

20. The method of claim 18, wherein

the forming of the channel layer and the gate insulating layer includes:

sequentially depositing an oxide semiconductor layer and an insulating layer on the insulating substrate; and

etching the insulating layer and the oxide semiconductor layer together.

21. The method of claim 18, wherein

the forming of the spacer includes:

forming a photosensitive film on the insulating layer;

exposing the photosensitive film using a half tone mask; and

developing the exposed the photosensitive film to form a spacer having a first portion disposed on the data line, and a second portion having a thicker thickness than the first portion.

22. The method of claim 18, further comprising:

forming a color filter on the pixel electrode.

23. The method of claim 18, further comprising:

forming a color filter between the interlayer insulating layer and the data line and pixel electrode.

24. The method of claim 18, further comprising:

forming a color filter before forming the channel layer.

25. A method for manufacturing a thin film transistor array panel comprising:

forming a channel layer including an oxide on an insulating substrate;

forming a gate insulating layer covering the channel layer;

forming a gate line including a gate electrode on the gate insulating layer;

forming an interlayer insulating layer on the gate line;

forming a plurality of contact holes exposing portions of the channel layer in the interlayer insulating layer and the gate insulating layer;

sequentially depositing a first conductive layer and a second conductive layer on the interlayer insulating layer;

forming a first photosensitive film pattern having a different thickness according to position on the second conductive layer;

etching the second conductive layer and the first conductive layer using the first photosensitive film pattern as an etching mask to form a data line including a source electrode, a drain electrode, and a previous pixel electrode connected to the drain electrode;

ashing the first photosensitive film pattern to form a second photosensitive film pattern exposing the second conductive layer of the previous pixel electrode;

etching the second conductive layer using the second photosensitive film pattern as an etching mask to form a pixel electrode;

forming a passivation layer on the data line, the drain electrode, and the pixel electrode; and

forming a spacer on the passivation layer.