POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS

• US 20080308903A1
• Filed: 06/15/2007
• Published: 12/18/2008
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Herner, S. Brad
• Granted Patent: US 8,004,013 B2
• Time in Patent Office: Days
• US Class Current: 257/565
• CPC Class Codes: G11C 11/416 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1022 including bipolar transistors
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.

Claims

1. A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises deposited silicon, germanium or silicon germanium crystallized in contact with a metal silicide, germanide or silicide-germanide.

2. The semiconductor device of claim 1 wherein the metal silicide, germanide, or silicide-germanide is titanium silicide.

3. The semiconductor device of claim 1 wherein the metal silicide, germanide, or silicide-germanide is titanium germanide.

4. The semiconductor device of claim 1 wherein the metal silicide, germanide, or silicide-germanide is titanium silicide germanide.

5. The semiconductor device of claim 1 wherein the emitter region and the collector region comprise deposited silicon, germanium or silicon germanium crystallized in contact with a metal silicide, germanide or silicide germanide.

6. The semiconductor device of claim 2 wherein the titanium silicide comprises C49 phase titanium silicide.

7. The semiconductor device of claim 6 wherein the titanium silicide is predominantly C49 phase titanium silicide.

8. The semiconductor device of claim 1 wherein the metal silicide, germanide, or silicide-germanide is cobalt silicide, cobalt germanide or cobalt silicide-germanide.

9. The semiconductor device of claim 1 wherein the transistor is a p-n-p bipolar transistor.

10. The semiconductor device of claim 1 wherein the transistor is a n-p-n bipolar transistor.

11. The semiconductor device of claim 1 wherein the transistor is disposed above a substrate, the transistor being in operative connection to a first memory cell formed above the substrate, wherein a first memory level monolithically formed above the substrate comprises the transistor and the first memory cell.

12. The semiconductor device of claim 11 wherein the substrate is a silicon wafer.

13. The semiconductor element of claim 11 wherein the substrate comprises one or more of glass, semiconductor material, metal, plastic, silicon dioxide and aluminum oxide.

14. The semiconductor device of claim 11 wherein the first memory cell comprises a diode.

15. The semiconductor device of claim 14 wherein the diode is a vertically oriented p-i-n diode.

16. The semiconductor device of claim 15 wherein a monolithic three dimensional array of memory cells comprises the first memory level.

17. The semiconductor device of claim 16 wherein the monolithic three dimensional memory array further comprising a second memory level monolithically formed above the first memory level.

18. The semiconductor device of claim 17, wherein one or more bipolar transistors are disposed at the first and second memory levels above the substrate and operatively connected to one or more of the memory cells within those memory levels.

19. The semiconductor device of claim 17 wherein the bipolar transistor is capable of selectively programming one or more of the diode memory cells.

20. The semiconductor device of claim 19 wherein the bipolar transistor is connected to a semiconductor element disposed on a substrate.

21. The semiconductor device of claim 20 wherein the semiconductor element comprises logic circuitry.

22. The semiconductor device of claim 20 wherein the semiconductor element comprises a CMOS gate.

23. A monolithic three dimensional memory array comprising:

a plurality of semiconductor elements in a stacked array above a substrate, the array comprising one or more device levels of semiconductor elements;

one or more thin film bipolar transistors disposed in the stacked array above the substrate, each semiconductor element being operatively connected to one or more of the bipolar transistors, wherein the bipolar transistors comprise deposited semiconductor material crystallized in contact with a silicide, germanide, or silicide-germanide.

24. The monolithic three dimensional memory array of claim 23 wherein at least one of the bipolar transistors is capable of selectively programming one or more memory cells.

25. The monolithic three dimensional memory array of claim 23 including at least one p-n-p bipolar transistor.

26. The monolithic three dimensional memory array of claim 23 wherein the substrate is a portion of a silicon wafer.

27. The monolithic three dimensional memory array of claim 23 wherein the substrate comprises one or more of glass, semiconductor material, metal, plastic, silicon dioxide and aluminum oxide.

28. The monolithic three dimensional memory array of claim 23 wherein the silicide, germanide, or silicide-germanide is titanium silicide.

29. The monolithic three dimensional memory array claim 28 wherein the titanium silicide is predominantly C49 phase titanium silicide.

30. The monolithic three dimensional memory array of claim 23 wherein the semiconductor elements comprise diodes.

31. The monolithic three dimensional memory array of claim 30 wherein the diodes comprise vertically oriented p-i-n diodes.

32. A monolithic three dimensional memory array comprising:

an array of multiple memory levels of memory cells stacked on a substrate, each memory level comprising a plurality of memory cell rows and memory cell columns; and

one or more thin film bipolar transistors disposed in the array above the substrate, in operative connection to one or more of the memory cells;

wherein the memory cells and transistors comprise deposited semiconductor material crystallized in contact with a silicide, germanide, or silicide-germanide.

33. The monolithic three dimensional memory array of claim 32 wherein the one or more bipolar transistor are p-n-p transistors.

34. The monolithic three dimensional memory array of claim 32 wherein the array includes wordlines extending along the memory rows and bitlines extending along the memory columns, and at least one bipolar transistor is located at an end of a bitline.

35. The monolithic three dimensional memory array of claim 32 wherein the array includes wordlines extending along the memory rows and bitlines extending along the memory columns, and at least one bipolar transistor is located at an end of a wordline.

36. The monolithic three dimensional memory array of claim 32 wherein the memory cells comprise vertically oriented diodes.

37. The monolithic three dimensional memory array of claim 36 wherein the diodes are p-i-n diodes.

38. The monolithic three dimensional memory array of claim 32 wherein the memory cells are one time programmable memory cells.

39. The monolithic three dimensional memory array of claim 38 wherein at least one of the memory cells includes an antifuse layer.

40. The monolithic three dimensional memory array of claim 39 wherein the antifuse layer comprises a high k dielectric.

41. The monolithic three dimensional memory array of claim 40 wherein the antifuse layer is selected from the group consisting of SiO_2, Al₂O₃, HfO₂ HfSiO₂, SiN, ZrO₂, TiO₂, or any mixture thereof.

42. The monolithic three dimensional memory array of claim 32 wherein the stacked array comprises at least three memory levels.

43. The monolithic three dimensional memory array of claim 32 wherein the substrate is a portion of a silicon wafer.

44. The monolithic three dimensional memory array of claim 32 wherein the substrate comprises one or more of glass, semiconductor material, metal, plastic, silicon dioxide and aluminum oxide.

45. The monolithic three dimensional memory array of claim 32 wherein one or more of the bipolar transistors are capable of selectively programming one or more of the memory cells.

46. The monolithic three dimensional memory array of claim 32 wherein the silicide, germanide, or silicide-germanide is titanium silicide.

47. The monolithic three dimensional memory array of claim 46 wherein the titanium silicide comprises C49 phase titanium silicide.

48. The three dimensional semiconductor device of claim 47 wherein the titanium silicide is predominantly C49 phase titanium silicide.