POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS
First Claim
1. A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises deposited silicon, germanium or silicon germanium crystallized in contact with a metal silicide, germanide or silicide-germanide.
4 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.
-
Citations
48 Claims
- 1. A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises deposited silicon, germanium or silicon germanium crystallized in contact with a metal silicide, germanide or silicide-germanide.
-
23. A monolithic three dimensional memory array comprising:
-
a plurality of semiconductor elements in a stacked array above a substrate, the array comprising one or more device levels of semiconductor elements; one or more thin film bipolar transistors disposed in the stacked array above the substrate, each semiconductor element being operatively connected to one or more of the bipolar transistors, wherein the bipolar transistors comprise deposited semiconductor material crystallized in contact with a silicide, germanide, or silicide-germanide. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A monolithic three dimensional memory array comprising:
-
an array of multiple memory levels of memory cells stacked on a substrate, each memory level comprising a plurality of memory cell rows and memory cell columns; and one or more thin film bipolar transistors disposed in the array above the substrate, in operative connection to one or more of the memory cells; wherein the memory cells and transistors comprise deposited semiconductor material crystallized in contact with a silicide, germanide, or silicide-germanide. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
-
Specification