SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

• US 20080308935A1
• Filed: 06/18/2008
• Published: 12/18/2008
• Est. Priority Date: 06/18/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: O, Min-Ho, LEE, Jong-Ho, KIM, Young-Lyong, AHN, Eun-Chul, YOUN, Cheul-Joong, YOON, Tae-Sung, YOO, Cheol-Joon
• Application Number:
  US12/141,764
• Publication Number:
  US 20080308935A1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP

Abstract

Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.

Claims

1. A semiconductor chip package comprising:

a semiconductor chip including a first surface, a second surface, and side surfaces, the first surface having bonding pads and the second surface facing the first surface;

bump solder balls provided on the bonding pads, the bump solder balls respectively including a section parallel to the first surface having a maximum diameter; and

a molding layer formed on the semiconductor chip to cover the first surface and expose portions of the bump solder balls, the molding layer between adjacent bump solder balls having a meniscus concave surface,

wherein a height from the first surface to an edge of the meniscus concave surface contacting a corresponding bump solder ball is about a 1/7 length of the maximum diameter of the corresponding bump solder ball at below or above the section of the bump solder ball having the maximum diameter.

2. The semiconductor chip package of claim 1, wherein the edge of the meniscus concave surface has a height of about 50 μ

m at below or above the section of the bump solder ball having the maximum diameter.

3. The semiconductor chip package of claim 1, wherein the meniscus concave surface comprises:

a first height from the first surface to the edge contacting the bump solder balls; and

a second height from the first surface to a central part between the bump solder balls.

4. The semiconductor chip package of claim 3, wherein a height difference between the first height and the second height is within about a ⅕

length of the maximum diameter of the bump solder ball.

5. The semiconductor chip package of claim 4, wherein the height difference is at least about 10 μ

m between the first height and the second height.

6. The semiconductor chip package of claim 1, wherein the meniscus concave surface has a matted surface.

7. The semiconductor chip package of claim 1, wherein the semiconductor chip has a thickness of about 50 μ

m to about 760 μ

m.

8. The semiconductor chip package of claim 1, wherein the bump solder balls comprise a solder material having a Young'"'"'s modulus of about 20 GPa to about 90 GPa.

9. The semiconductor chip package of claim 1, wherein the molding layer comprises an epoxy molding compound (EMC).

10. The semiconductor chip package of claim 9, wherein the EMC comprises silica of about 50 wt % to about 90 wt %.

11. The semiconductor chip package of claim 9, wherein the EMC has a thermal expansion coefficient of below about 50 ppm/°

C. at a temperature range of less than a glass transition temperature.

12. The semiconductor chip package of claim 9, wherein the EMC has an elastic modulus of more than about 3 GPa.

13. The semiconductor chip package of claim 1, wherein the molding layer is provided to cover the side surfaces of the semiconductor chip.

14. The semiconductor chip package of claim 1, further comprising a passivation layer provided on the second surface of the semiconductor chip.

15. The semiconductor chip package of claim 14, wherein the passivation layer has a thickness of about 20 μ

m to about 700 μ

m.

16. The semiconductor chip package of claim 14, wherein the passivation layer is an EMC or a resin-based material.

17. The semiconductor chip package of claim 14, wherein the passivation layer comprises substantially the same material as the molding layer.

18. The semiconductor chip package of claim 1, further comprising a carrier layer provided on the second surface of the semiconductor chip.

19. The semiconductor chip package of claim 18, wherein the carrier layer comprises at least one of a metal material, a ceramic material, or an organic material.

20. A semiconductor package comprising:

the semiconductor chip package of claim 1; and

a wiring substrate including a first surface and a second surface, the first surface on which the semiconductor chip package is mounted, the second surface facing the first surface.

21. The semiconductor package of claim 20, further comprising wiring substrate solder balls provided on the second surface of the wiring substrate.

22. A method of fabricating a semiconductor chip package, the method comprising:

preparing a semiconductor chip group that includes at least one semiconductor chip, the semiconductor chip including a first surface with bonding pads, a second surface facing the first surface, and side surfaces;

forming bump solder balls on the bonding pads, the bump solder balls each including a section parallel to the first surface and having a maximum diameter; and

forming a molding layer to cover the first surface and expose respective portions of the bump solder balls,

the molding layer between adjacent bump solder balls formed to have a meniscus concave surface,

wherein a height from the first surface to an edge of the meniscus concave surface contacting a corresponding bump solder ball is about a 1/7 length of the maximum diameter of the corresponding bump solder ball at below or above the section of the bump solder ball having the maximum diameter.

23. The method of claim 22, wherein the edge of the meniscus concave surface has a height of about 50 μ

m at below or above the section of the bump solder ball having the maximum diameter.

24. The method of claim 22, wherein the meniscus concave surface comprises:

a first height from the first surface to the edge contacting the bump solder balls; and

a second height from the first surface to a central part between the bump solder balls.

25. The method of claim 24, wherein a height difference between the first height and the second height is within about a ⅕

length of the maximum diameter of the bump solder ball.

26. The method of claim 25, wherein the height difference is at least about 10 μ

m between the first height and the second height.

27. The method of claim 22, wherein the meniscus concave surface has a matted surface.

28. The method of claim 22, further comprising polishing the second surface of the semiconductor chip.

29. The method of claim 28, wherein the polished semiconductor chip has a thickness of about 50 μ

m to about 760 μ

m.

30. The method of claim 22, wherein the bump solder balls comprise a solder material having a Young'"'"'s modulus of about 20 GPa to about 90 GPa.

31. The method of claim 22, wherein the forming of the molding layer comprises:

preparing a release tape;

loading the semiconductor chip group;

injecting a molding material between the release tape and the semiconductor chip group; and

compressing the semiconductor chip group and the release tape, respectively.

32. The method of claim 31, wherein:

the release tape is prepared between a lower mold and an upper mold, the lower mold having a molding part, the upper mold facing the lower mold and having a mounting part;

the molding material is injected on the molding part to be provided on the release tape;

the semiconductor chip group is loaded into the mounting part; and

the compressing of the semiconductor chip group and the release tape includes contacting the upper mold and the lower mold.

33. The method of any one of claims 32, further comprising pre-heating and vacuum-discharging the molding part after the injecting of the molding material.

34. The method of claim 31, wherein:

the release tape is prepared between a lower mold and an upper mold, the lower mold having a molding part with a mounting part, the upper mold facing the lower mold;

the semiconductor chip group is loaded into the mounting part;

the molding material is injected on the molding part to be provided on the bump solder balls; and

the compressing of the semiconductor chip group and the release tape includes contacting the upper mold and the lower mold.

35. The method of any one of claims 34, further comprising pre-heating and vacuum-discharging the molding part after the injecting of the molding material.

36. The method of claim 31, wherein a thickness of the release tape is greater than a value subtracting the second height of the molding layer from the height of the bump solder ball.

37. The method of claim 36, wherein the release tape has a matted surface.

38. The method of claim 36, wherein the release tape is a polytetrafluoroethylene (PTFE) or an ethylene tetrafluoroethylene (ETFE) copolymer.

39. The method of claim 38, wherein the release tape has an elongation of about 10% to about 900% and a tensile stress of below about 50 MPa.

40. The method of claim 31, wherein the molding material comprises an EMC.

41. The method of claim 40, wherein the EMC has a powder form or a liquid form.

42. The method of claim 41, wherein the EMC comprises silica of about 50 wt % to about 90 wt %.

43. The method of claim 41, wherein the EMC has a thermal expansion coefficient of below about 50 ppm/°

C. at a temperature range of less than a glass transition temperature.

44. The method of claim 22, wherein the molding layer is provided to cover the side surfaces of the semiconductor chip.

45. The method of claim 28, further comprising forming a passivation layer on the second surface of the polished semiconductor chip.

46. The method of claim 45, wherein the passivation layer has a thickness of about 20 μ

m to about 700 μ

m.

47. The method of claim 45, wherein the passivation layer is an EMC or a resin-based material.

48. The method of claim 45, wherein the passivation layer comprises substantially the same material as the molding layer.

49. The method of claim 28, further comprising forming a carrier layer on the second surface of the polished semiconductor chip.

50. The method of claim 49, wherein the carrier layer comprises at least one of a metal material, a ceramic material, or an organic material.

51. The method of claim 22, wherein if the semiconductor chip group includes a plurality of semiconductor chips, the semiconductor chip group has one of a wafer form, a strip form, and a carrier mounted form, the wafer form having scribe lanes between the semiconductor chips.

52. The method of claim 51, further comprising cutting the scribe lanes between the semiconductor chips and the molding layer to separate the semiconductor chip group into a plurality of semiconductor chip packages.

53. A method of fabricating a semiconductor package, the method comprising:

preparing a semiconductor chip package fabricated using the method of claim 22;

preparing a wiring substrate having a first surface and a second surface, the first surface on which the semiconductor chip package is mounted, the second surface facing the first surface; and

mounting the semiconductor chip package on the first surface of the wiring substrate.

54. The method of claim 53, further comprising forming wiring substrate solder balls on the second surface.