SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES

• US 20080308946A1
• Filed: 06/15/2007
• Published: 12/18/2008
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, David A.
• Granted Patent: US 8,367,471 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Claims

1. A method of manufacturing stacked semiconductor assemblies, comprising:

mounting a semiconductor wafer to a temporary carrier wherein the wafer has a plurality of first dies arranged in a die pattern on the wafer;

thinning the wafer;

attaching a plurality of singulated second dies to corresponding first dies, wherein the second dies are arranged in the die pattern and spaced apart from each other by gaps;

disposing an encapsulating material in the gaps between the second dies; and

thinning the second dies after attaching the second dies to the first dies.

2. The method of claim 1, wherein thinning the second dies includes grinding a back side of the second dies.

3. The method of claim 1, further comprising cutting through the encapsulating material in the gaps and cutting the wafer to singulate stacked microelectronic devices having a first die and a corresponding second die.

4. The method of claim 1 wherein:

individual first and second dies include an integrated circuit and a terminal electrically coupled to the integrated circuit; and

before mounting the wafer to the temporary carrier, the method further comprises forming an interconnect in at least a portion of the individual first dies in electrical contact with the terminal;

thinning the wafer comprises simultaneously exposing a plurality of first die interconnects at a back side of the wafer that define external contacts; and

attaching the second dies to the first dies further comprises electrically coupling front side terminals of the second dies to corresponding external contacts at the back side of the wafer.

5. The method of claim 1 wherein:

before attaching the plurality of second dies to corresponding first dies, the method further comprises testing individual first dies and individual second dies to determine known good first and second dies and known bad first and second dies; and

attaching the second dies to corresponding first dies comprises attaching known good second dies to known good first dies and attaching known bad second dies to known bad first dies to form a plurality of known good stacked devices and a plurality of known bad stacked devices.

6. The method of claim 1, further comprising:

attaching singulated third dies to corresponding second dies such that the third dies are spaced apart from each other by gaps;

disposing additional encapsulant material in the gaps between the third dies; and

removing material from a back side of the third dies after disposing the encapsulant material in the gaps between the third dies.

7. The method of claim 1 wherein the individual second dies have a handling thickness when the second dies are attached to the first dies, and thinning the second dies comprises reducing the thickness of the second dies to about 20-150 microns.

8. The method of claim 1 wherein the individual second dies have a handling thickness when the second dies are attached to the first dies, and thinning the second dies comprises reducing the thickness of the second dies to less than 100 microns.

9. The method of claim 1 wherein the wafer has an initial thickness before thinning of approximately 700-1000 microns, and thinning the wafer comprises reducing the thickness to approximately less than 50 microns, wherein the individual second dies have a handling thickness greater than 150 microns when the second dies are attached to the first dies, and thinning the second dies comprises reducing the thickness of the second dies to about 20-150 microns.

10. A method of manufacturing semiconductor workpieces, comprising:

reducing an initial thickness of a semiconductor wafer between a front side of the wafer and a back side of the wafer, wherein the wafer has a plurality of first dies and first interconnects;

mounting a plurality of separated second dies to corresponding first dies in a stacked configuration to form a plurality of stacked microelectronic devices, wherein individual second dies have second interconnects connected to terminals on a first side of the second die and extending to an intermediate level such that the second interconnects are not exposed on a second side of the second die opposite the first side;

at least partially encapsulating the stacked devices; and

thinning the second dies and exposing the second interconnects on the second side after at least partially encapsulating the stacked devices.

11. The method of claim 10 wherein reducing the initial thickness of the semiconductor wafer comprises reducing the initial thickness between the front side and the back side to approximately less than 100 microns, and wherein thinning the second dies comprises reducing a second die thickness between the first and second sides to less than 300 microns.

12. The method of claim 11 wherein;

before mounting the plurality of second dies to corresponding first dies, the method further comprises testing individual first dies and individual second dies to determine known good first and second dies and known bad first and second dies; and

mounting the second dies to corresponding first dies comprises mounting known good second dies to known good first dies arranged in a stacked configuration and mounting known bad second dies to known bad first dies arranged in a stacked configuration to form a plurality of known good stacked devices and known bad stacked devices.

13. The method of claim 10 wherein thinning the second dies comprises simultaneously thinning the second dies to a thickness between the first and second sides of approximately less than 300 microns.

14. The method of claim 10 wherein:

before encapsulating the stacked devices, the method further comprises dispensing an underfill material between the second dies and the wafer; and

thinning the second dies includes grinding the second sides of the second dies while in a stacked configuration.

15. The method of claim 11 wherein the initial thickness of the semiconductor wafer is approximately 500-1000 microns and the second die have thickness of approximately 500-1000 microns after the mounting stage but before the thinning stage.

16. A method of manufacturing semiconductor assemblies, the method comprising:

forming first and second semiconductor wafers having front sides and back sides opposite the front sides and an array of dies at the front sides arranged in a die pattern, the individual dies including an integrated circuit and a terminal electrically coupled to the integrated circuit;

forming a plurality of interconnects in electrical contact with the die terminals on the first and second wafers;

attaching a carrier substrate to the front side of the first wafer;

processing the back side of the first wafer to form a thinned base wafer with exposed interconnect studs;

dividing the second wafer to form singulated second dies;

populating the first dies with singulated second dies to form an array of stacked semiconductor devices in the die pattern, wherein the terminals on the front side of the second dies are electrically coupled with the corresponding interconnect studs of the first dies;

at least partially encapsulating the stacked devices; and

grinding the back side of the second dies after encapsulating the stacked devices.

17. The method of claim 16 wherein;

before populating the first dies with the second dies, the method further comprises testing individual first dies and second dies to determine known good first and second dies and known bad first and second dies; and

populating the first dies with second dies comprises attaching known good second dies to known good first dies arranged in a stacked configuration and attaching known bad second dies to known bad first dies arranged in a stacked configuration to form a plurality of known good stacked devices and known bad stacked devices.

18. A semiconductor assembly, comprising:

a thinned semiconductor wafer having an active side, a back side opposite the active side, and a plurality of first dies arranged in a die pattern at the active side, wherein individual first dies have an integrated circuit and first through die interconnects electrically connected to the integrated circuit, and wherein the first through die interconnects have interconnect contacts exposed at the back side of the wafer; and

a plurality of separate second dies spaced apart from each other and arranged in the die pattern relative to the thinned semiconductor wafer, individual second dies having a second active side, a second back side, a second integrated circuit, and a second terminal electrically coupled to the second integrated circuit on the second active side, wherein the individual second dies have a thickness of approximately less than 150 microns.

19. The assembly of claim 18, further comprising an underfill deposited between the first and second dies.

20. The assembly of claim 18 wherein the thickness of the plurality of second dies is substantially uniform across the thinned semiconductor wafer.

21. The assembly of claim 18 wherein the thinned semiconductor wafer has a thickness of approximately less than 100 microns.

22. The assembly of claim 18 wherein the thinned semiconductor wafer has a wafer thickness of approximately less than 50 microns and the thickness of the second die is approximately less than 50 microns.

23. The assembly of claim 18, further comprising:

a plurality of separate third dies spaced apart from each other and arranged in the die pattern relative to the thinned semiconductor wafer, individual third dies having a third active side, a third back side, a third integrated circuit, a third terminal electrically coupled to the third integrated circuit on the third active side, wherein the third die has a thickness of approximately less than 100 microns.

24. An intermediate stacked semiconductor assembly, comprising:

a thinned semiconductor wafer having an active side, a plurality of first dies arranged in a die pattern, and first through die interconnects extending from the active side to a back side of the wafer;

a plurality of singulated second dies mounted to corresponding first dies, wherein the individual second dies are spaced apart from each other by gaps, and wherein the second dies have a first side, a second side spaced apart from the first side by a handling thickness, and a second interconnect extending from the first side to an intermediate depth in the second die such that the second interconnects are not exposed on the second side of the second dies; and

an encapsulant in the gaps.

25. The assembly of claim 24 wherein the individual second dies have a handling thickness approximately greater than 300 microns.

26. The assembly of claim 24 wherein the thinned semiconductor wafer has a final thickness approximately less than 50 microns.

27. A semiconductor assembly, comprising:

a wafer including a plurality of known good first dies and a plurality of known bad first dies;

a plurality of separated known good second dies attached to corresponding known good first dies, and a plurality of separated known bad second dies attached to corresponding known bad first dies, wherein the second dies are spaced apart from each other by gaps; and

an encapsulant material in the gaps.

28. The assembly of claim 27 wherein the wafer has a thickness approximately less than 100 microns.

29. The assembly of claim 27 wherein the separated second dies have a thickness approximately less than 100 microns.

30. The assembly of claim 27 wherein known good first dies individually comprise a first integrated circuit electrically coupled to a first terminal and a through die interconnect, and wherein known good second dies individually comprise a second terminal electrically coupled to a second integrated circuit and an interconnect contact point of the corresponding through die interconnect.