Semiconductor package and method for manufacturing thereof

• US 20080308950A1
• Filed: 02/12/2008
• Published: 12/18/2008
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Choi, Seog-Moon, Jeong, Tae-Sung, Kweon, Young Do, Jang, Burn-Sik, Yoo, Do Jae
• Granted Patent: US 7,642,656 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.

Claims

1. A semiconductor package comprising:

a first substrate having a pre-designed pattern formed thereon;

a first chip mounted by a flip chip method on one side of the first substrate;

a first molding covering the first substrate and the first chip;

a first via penetrating the first molding and electrically connected with the pattern formed on the first substrate;

an interposer placed on the first molding and having a pre-designed pattern formed respectively on both sides thereof;

a second via penetrating the interposer and electrically connecting both sides of the interposer;

a second substrate placed on the interposer with at least one conductive ball positioned in-between such that the second substrate is electrically connected with the pattern formed on the interposer; and

a second chip mounted on the second substrate.

2. The semiconductor package of claim 1, wherein the interposer is a metal oxide layer.

3. The semiconductor package of claim 2, wherein the interposer is made of aluminum oxide (Al₂O₃).

4. The semiconductor package of claim 1, further comprising:

a passive component mounted on the first substrate.

5. The semiconductor package of claim 1, wherein the first via is a solder bump.

6. The semiconductor package of claim 1, wherein the second chip is connected to the second substrate by a wire bonding method,

and the semiconductor package further comprises a second molding covering the second chip and the second substrate.

7. The semiconductor package of claim 1, further comprising:

a plurality of conductive balls formed on the other side of the first substrate.

8. A method of manufacturing a semiconductor package, the method comprising:

mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon;

forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate;

forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip;

placing an interposer on the first molding; and

placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.

9. The method of claim 8, further comprising, after forming the first molding:

grinding a portion of the first molding.

10. The method of claim 8, wherein the interposer is a metal oxide layer.

11. The method of claim 10, wherein the interposer is made of aluminum oxide (Al₂O₃).

12. The method of claim 10, further comprising:

mounting at least one passive component on one side of the first substrate.

13. The method of claim 10, further comprising:

coupling a plurality of conductive balls onto the other side of the first substrate.

14. A semiconductor package comprising:

a first substrate having a pre-designed pattern formed thereon;

a first chip mounted by a flip chip method on one side of the first substrate;

a support formed to a predetermined thickness on an edge of the first substrate;

an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof;

a via penetrating the support and the interposer;

a second chip mounted on one side of the interposer facing the first substrate;

a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and

a third chip mounted on the second substrate.

15. The semiconductor package of claim 14, wherein the interposer is a metal oxide layer.

16. The semiconductor package of claim 15, wherein the interposer is made of aluminum oxide (Al₂O₃).

17. The semiconductor package of claim 14, further comprising:

a passive component mounted on the first substrate.

18. The semiconductor package of claim 14, further comprising:

a plurality of conductive balls formed on the other side of the first substrate.

19. A method of manufacturing a semiconductor package, the method comprising:

mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon;

forming a cavity by etching a center portion of a metal oxide layer;

mounting a second chip inside the cavity;

forming at least one via such that the via penetrates an edge of the metal oxide layer;

placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and

placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon.

20. The method of claim 19, wherein the metal oxide layer is made of aluminum oxide (Al₂O₃).

21. The method of claim 19, further comprising:

mounting at least one passive component on the first substrate.

22. The method of claim 19, further comprising:

coupling a plurality of conductive balls onto the other side of the first substrate.