High accuracy current mode duty cycle and phase placement sampling circuit
First Claim
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1. A signal sampling circuit comprising:
- a primary differential input stage to receive a first input signal and a second input signal, the primary differential input stage being enabled responsive to a first control signal to couple a first current through a first output node and couple a second current through a second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node and to limit the combination of the first current and the second current according to a bias signal;
a secondary differential input stage to receive a third input signal and a fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through the first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node and to limit the combination of the third current and the fourth current according to the bias signal;
first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal being de-asserted;
first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and
first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.
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Abstract
A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.
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Citations
34 Claims
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1. A signal sampling circuit comprising:
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a primary differential input stage to receive a first input signal and a second input signal, the primary differential input stage being enabled responsive to a first control signal to couple a first current through a first output node and couple a second current through a second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node and to limit the combination of the first current and the second current according to a bias signal; a secondary differential input stage to receive a third input signal and a fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through the first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node and to limit the combination of the third current and the fourth current according to the bias signal; first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal being de-asserted; first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. (canceled)
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9. (canceled)
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10. A data transmitter system, comprising:
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a clock generator; a first clock adjustment module coupled to the clock generator; a phase interpolator coupled to the first clock adjustment module; a second clock adjustment module coupled to the phase interpolator; a control module coupled to the first and second clock adjustment modules and operable to generate a first and a second control signal, the control module further operable to generate correction signals responsive to at least two error signals; a data serializer coupled to the second clock adjustment module and operable to serialize and transmit data; and a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the first and the second clock adjustment modules, the duty cycle and phase placement sampler operable to assert the at least two error signals on the first and second output nodes, respectively, indicative of duty cycle and phase placement errors, comprising; a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting the first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal; a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting the second control signal to couple a third current through first output node- and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal; first and second pre-charge transistors, the first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting; first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A clock correction circuit operable to accept a global clock signal and to generate a corrected clock signal, comprising:
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a clock generator to accept the global clock signal and operable to generate an internal clock signal from the global clock signal; a clock adjustment module coupled to the clock generator and operable to generate a corrected clock signal from the internal clock signal responsive to at least one correction signal; a control module coupled to the clock adjustment module, the control module operable to generate the at least one correction signal responsive to a differential error signal; and a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the clock adjustment module, the duty cycle and phase placement sampler operable to assert the differential error signal on the first and second output nodes indicative of duty cycle and phase placement errors in the input signals, comprising; a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting a first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal; a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal; first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting; first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage. - View Dependent Claims (17, 18, 19)
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21. A method for sampling a signal, comprising:
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changing a charge on first and second capacitors, the capacitors coupled to first and second output nodes, respectively; staffing at a first time, coupling a first current through the first and second output nodes through a first circuit branch according to a first and a second signal; starting at a second time, coupling a second current through the first and second output nodes through a second circuit branch according a third and a fourth signal; and driving the first and second output nodes to complementary logic levels, respectively, responsive to detecting a voltage difference between first and second output nodes. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A test system configured to test a device under test comprising:
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testing circuitry operable to generate test data, to receive responses to the test data, and to provide test results based on the responses; and a data transmitter comprising; a clock generator; a first clock adjustment module coupled to the clock generator; a phase interpolator coupled to the first clock adjustment module; a second clock adjustment module coupled to the phase interpolator; a control module coupled to the first and second clock adjustment modules and operable to generate a first and a second control signal, the control module further operable to generate correction signals responsive to at least two error signals; a data serializer coupled to the second clock adjustment module and operable to serialize and transmit the test data to the device under test; and a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the first and the second clock adjustment modules, the duty cycle and phase placement sampler operable to assert the at least two error signals on the first and second output nodes, respectively, indicative of duty cycle and phase placement errors, comprising; a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting the first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal; a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting the second control signal to couple a third current through first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal; first and second pre-charge transistors, the first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting; first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage. - View Dependent Claims (20, 30, 31, 32, 33, 34)
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Specification