High accuracy current mode duty cycle and phase placement sampling circuit

• US 20080309375A1
• Filed: 06/12/2007
• Published: 12/18/2008
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Schnarr, Curt
• Granted Patent: US 7,514,991 B2
• Time in Patent Office: Days
• US Class Current: 327/2
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.

Claims

1. A signal sampling circuit comprising:

a primary differential input stage to receive a first input signal and a second input signal, the primary differential input stage being enabled responsive to a first control signal to couple a first current through a first output node and couple a second current through a second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node and to limit the combination of the first current and the second current according to a bias signal;

a secondary differential input stage to receive a third input signal and a fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through the first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node and to limit the combination of the third current and the fourth current according to the bias signal;

first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal being de-asserted;

first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and

first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.

2. The signal sampling circuit of claim 1 further comprising:

a first differential flip-flop to receive a pre-charge signal and its complement as a first set of differential input signals and configured to latch the differential input signals on the rising edge of first input signal to produce a first set of differential output signals;

a second differential flip-flop to accept the first set of differential output signals from the first differential flip-flop as a second set of differential input signals and configured to latch the second set of differential input signals on the rising edge of the fourth input signal to produce a second set of differential output signals;

a first differential to single-ended converter configured to convert the first set of differential output signals into a first single-ended output signal; and

a second differential to single-ended converter configured to convert the second set of differential output signals into a second single-ended output signal.

3. The signal sampling circuit of claim 2 wherein the first single-ended output signal is the first control signal and the second single-ended output signal is the second control signal.

4. The signal sampling circuit of claim 3 further comprising:

a first differential 2-input AND gate configured to accept a first and second set of differential clock phase signals and logically AND the signals to produce a first output signal and a second output signal wherein the second output signal is the complement of the first output signal; and

a second differential 2-input AND gate configured to accept a third and fourth set of differential clock phase signals and logically AND the signals to produce a third output signal and a fourth output signal wherein the fourth output signal is the complement of the third output signal.

5. The signal sampling circuit of claim 4 wherein the first, second, third and fourth output signals from the AND gates serve as the first, second, fourth and third input signals, respectively.

6. The signal sampling circuit of claim 5 wherein the first set of differential clock phase signals is selected from among a plurality of complementary clock phase signals.

7. The signal sampling circuit of claim 6 wherein the second set of differential clock phase signals is selected from among a plurality of complementary clock phase signals.

8. (canceled)

9. (canceled)

10. A data transmitter system, comprising:

a clock generator;

a first clock adjustment module coupled to the clock generator;

a phase interpolator coupled to the first clock adjustment module;

a second clock adjustment module coupled to the phase interpolator;

a control module coupled to the first and second clock adjustment modules and operable to generate a first and a second control signal, the control module further operable to generate correction signals responsive to at least two error signals;

a data serializer coupled to the second clock adjustment module and operable to serialize and transmit data; and

a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the first and the second clock adjustment modules, the duty cycle and phase placement sampler operable to assert the at least two error signals on the first and second output nodes, respectively, indicative of duty cycle and phase placement errors, comprising;

a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting the first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal;

a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting the second control signal to couple a third current through first output node- and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal;

first and second pre-charge transistors, the first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting;

first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and

first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.

11. The data transmitter system of claim 10 further comprising:

a first differential flip-flop to receive a pre-charge signal and its complement as a first set of differential input signals and configured to latch the differential input signals on the rising edge of first input signal to produce a first set of differential output signals;

a second differential flip-flop to accept the first set of differential output signals from the first differential flip-flop as a second set of differential input signals and configured to latch the second set of differential input signals on the rising edge of the fourth input signal to produce a second set of differential output signals;

a first differential to single-ended converter configured to convert the first set of differential output signals into a first single-ended output signal; and

a second differential to single-ended converter configured to convert the second set of differential output signals into a second single-ended output signal.

12. The data transmitter system of claim 11 wherein the first single-ended output signal is the first control signal and the second single-ended output signal is the second control signal.

13. The data transmitter system of claim 12 further comprising:

a first differential 2-input AND gate configured to accept a first and second set of differential clock phase signals and logically AND the signals to produce a first output signal and a second output signal wherein the second output signal is the complement of the first output signal; and

a second differential 2-input AND gate configured to accept a third and fourth set of differential clock phase signals and logically AND the signals to produce a third output signal and a fourth output signal wherein the fourth output signal is the complement of the third output signal.

14. The data transmitter system of claim 13 wherein the first, second, third and fourth output signals from the AND gates serve as the first, second, fourth and third input signals, respectively.

15. The data transmitter system of claim 14 wherein the first and second set of differential clock phase signals is selected from among a plurality of complementary clock phase signals.

16. A clock correction circuit operable to accept a global clock signal and to generate a corrected clock signal, comprising:

a clock generator to accept the global clock signal and operable to generate an internal clock signal from the global clock signal;

a clock adjustment module coupled to the clock generator and operable to generate a corrected clock signal from the internal clock signal responsive to at least one correction signal;

a control module coupled to the clock adjustment module, the control module operable to generate the at least one correction signal responsive to a differential error signal; and

a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the clock adjustment module, the duty cycle and phase placement sampler operable to assert the differential error signal on the first and second output nodes indicative of duty cycle and phase placement errors in the input signals, comprising;

a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting a first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal;

a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting a second control signal to couple a third current through first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal;

first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting;

first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and

first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.

17. The clock correction circuit of claim 16 further comprising:

a first differential flip-flop to receive a pre-charge signal and its complement as a first set of differential input signals and configured to latch the differential input signals on the rising edge of first input signal to produce a first set of differential output signals;

a second differential flip-flop to accept the first set of differential output signals from the first differential flip-flop as a second set of differential input signals and configured to latch the second set of differential input signals on the rising edge of the fourth input signal to produce a second set of differential output signals;

a first differential to single-ended converter configured to convert the first set of differential output signals into a first single-ended output signal; and

a second differential to single-ended converter configured to convert the second set of differential output signals into a second single-ended output signal.

18. The clock correction circuit of claim 17 wherein the first single-ended output signal is the first control signal and the second single-ended output signal is the second control signal.

19. The clock correction circuit of claim 18 further comprising:

a first differential 2-input AND gate configured to accept a first and second set of differential clock phase signals and logically AND the signals to produce a first output signal and a second output signal wherein the second output signal is the complement of the first output signal; and

a second differential 2-input AND gate configured to accept a third and fourth set of differential clock phase signals and logically AND the signals to produce a third output signal and a fourth output signal wherein the fourth output signal is the complement of the third output signal.

21. A method for sampling a signal, comprising:

changing a charge on first and second capacitors, the capacitors coupled to first and second output nodes, respectively;

staffing at a first time, coupling a first current through the first and second output nodes through a first circuit branch according to a first and a second signal;

starting at a second time, coupling a second current through the first and second output nodes through a second circuit branch according a third and a fourth signal; and

driving the first and second output nodes to complementary logic levels, respectively, responsive to detecting a voltage difference between first and second output nodes.

22. The method of claim 21 wherein coupling the first current through the first and second output nodes further comprises:

coupling a portion of the first current through the first output node responsive to the first signal; and

coupling a portion of the first current through the second output node responsive to the second signal.

23. The method of claim 22 wherein coupling the second current through the first and second output nodes further comprises:

coupling a portion of the second current through the first output node responsive to the third signal; and

coupling a portion of the second current through the second output node responsive to the fourth signal.

24. The method of claim 23 wherein the second time is after the first time.

25. The method of claim 24 further comprising:

logically AND'"'"'ing a first and a second differential clock phase signal to provide a first complementary result signal; and

logically AND'"'"'ing a third and fourth differential clock phase signal to provide a second complementary result signal.

26. The method of claim 25 wherein the first and second signals are the true and complement halves of the first complementary result signal.

27. The method of claim 26 wherein the third and fourth signals are the true and complement halves of the second complementary result signal.

28. The method of claim 27 wherein the first, second, third and fourth differential clock phase signals are selected from among a plurality of complementary clock phase signals.

29. A test system configured to test a device under test comprising:

testing circuitry operable to generate test data, to receive responses to the test data, and to provide test results based on the responses; and

a data transmitter comprising;

a clock generator;

a first clock adjustment module coupled to the clock generator;

a phase interpolator coupled to the first clock adjustment module;

a second clock adjustment module coupled to the phase interpolator;

a control module coupled to the first and second clock adjustment modules and operable to generate a first and a second control signal, the control module further operable to generate correction signals responsive to at least two error signals;

a data serializer coupled to the second clock adjustment module and operable to serialize and transmit the test data to the device under test; and

a duty cycle and phase placement sampler coupled to the control module by at least a first and a second output node and configured to accept first, second, third and fourth input signals from the first and the second clock adjustment modules, the duty cycle and phase placement sampler operable to assert the at least two error signals on the first and second output nodes, respectively, indicative of duty cycle and phase placement errors, comprising;

a primary differential input stage to receive the first input signal and the second input signal, the primary differential input stage being enabled by asserting the first control signal to couple a first current through the first output node and couple a second current through the second output node in response to the first and second input signals, respectively, the primary differential input stage being configured to limit the first current according to the voltage of the second output node, to limit the second current according to the voltage of the first output node, and to limit the combination of the first current and the second current according to a bias signal;

a secondary differential input stage to receive the third input signal and the fourth input signal, the secondary differential input stage being enabled by asserting the second control signal to couple a third current through first output node and couple a fourth current through the second output node in response to the third and fourth input signals, respectively, the secondary differential input stage being configured to limit the third current according to the voltage of the second output node, to limit the fourth current according to the voltage of the first output node, and to limit the combination of the third current and the fourth current according to the bias signal;

first and second pre-charge transistors, the first and second pre-charge transistors operable to couple a first voltage to the first output node and to the second output node, respectively, responsive to the first control signal de-asserting;

first and second feedback transistors, the first feedback transistor operable to couple the first voltage to the first output node according to the voltage of the second output node and the second feedback transistor operable to couple the first voltage to the second output node according to the voltage of the first output node; and

first and second integrating capacitors, the first and second integrating capacitors coupled to the first and second output nodes, respectively, and each further configured to be coupled to a second voltage.

20. The clock correction circuit of claim 29 wherein the first and second set of differential clock phase signals is selected from among a plurality of complementary clock phase signals.

30. The test system of claim 29 wherein the data transmitter further comprises:

a first differential flip-flop to receive a pre-charge signal and its complement as a first set of differential input signals and configured to latch the differential input signals on the rising edge of first input signal to produce a first set of differential output signals;

a second differential flip-flop to accept the first set of differential output signals from the first differential flip-flop as a second set of differential input signals and configured to latch the second set of differential input signals on the rising edge of the fourth input signal to produce a second set of differential output signals;

a first differential to single-ended converter configured to convert the first set of differential output signals into a first single-ended output signal; and

a second differential to single-ended converter configured to convert the second set of differential output signals into a second single-ended output signal.

31. The test system of claim 30 wherein the first and second single-ended output signals of the data transmitter are the first control signal and the second control signals of the data transmitter, respectively.

32. The test system of claim 31 wherein the data transmitter further comprises:

a first differential 2-input AND gate configured to accept a first and second set of differential clock phase signals and logically AND the signals to produce a first output signal and a second output signal wherein the second output signal is the complement of the first output signal; and

a second differential 2-input AND gate configured to accept a third and fourth set of differential clock phase signals and logically AND the signals to produce a third output signal and a fourth output signal wherein the fourth output signal is the complement of the third output signal.

33. The test system of claim 32 wherein the first, second, third and fourth output signals from the AND gates serve as the first, second, fourth and third input signals, respectively.

34. The test system of claim 33 wherein the first and second set of differential clock phase signals is selected from among a plurality of complementary clock phase signals.