Method and apparatus for improving the light load efficiency of a switching mode converter

• US 20080310194A1
• Filed: 06/10/2008
• Published: 12/18/2008
• Est. Priority Date: 06/13/2007
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Huang, Pei-Lun, Tai, Liang-Pin
• Granted Patent: US 8,031,493 B2
• Time in Patent Office: Days
• US Class Current: 363/21.18
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A method and apparatus are provided for a switching mode converter to improve the light load efficiency thereof. The converter is thus operated with three modes by monitoring a feedback signal and a supply voltage. When the feedback signal indicates that loading gets light enough, the converter is switched from the first mode to the second mode, and during the second mode some cycles are skipped. If loading is too light, the converter is switched from the second mode to the third mode, and during the third mode more cycles will be skipped.

Claims

1. A method for improving the light load efficiency of a switching mode converter having a controller to provide a switching signal to switch a power switch so as to regulate an output voltage supplied for load, the controller using a clock to trigger the switching signal and receiving a supply voltage dependent on the switching of the power switch, the method comprising the steps of:

monitoring the output voltage to thereby generate a feedback signal; and

operating the converter with a first mode, a second mode or a third mode according to the feedback signal and the supply voltage;

wherein during the first mode, if the feedback signal decreases to a lower threshold due to load decreasing, the converter is switched to the second mode from the first mode, and during the second mode, if loading further decreases to cause the supply voltage decreasing to a lower limit, the converter is switched to the third mode from the second mode.

2. The method of claim 1, wherein during the first mode the power switch is periodically switched by the switching signal.

3. The method of claim 1, wherein during the second mode the power switch is turned off for a period of time after each time it is continuously switched for a plurality of cycles.

4. The method of claim 1, wherein during the second mode the clock or the switching signal is blanked when the feedback signal decreases to the lower threshold and released when the feedback signal increases to an upper threshold.

5. The method of claim 1, wherein during the third mode the power switch is forced to be switched when the supply voltage is lower than the lower limit.

6. The method of claim 1, wherein during the third mode the clock or the switching signal is released when the supply voltage decreases to the lower limit and blanked when the supply voltage increases to an upper limit.

7. An apparatus for improving the light load efficiency of a switching mode converter having a controller to provide a switching signal to switch a power switch so as to regulate an output voltage supplied for load, the controller using a clock to trigger the switching signal and receiving a feedback signal dependent on the output voltage and a supply voltage dependent on the switching of the power switch, the apparatus comprising:

a first comparator for comparing the feedback signal with a lower threshold to thereby determine a first comparison signal;

a second comparator for comparing the feedback signal with an upper threshold to thereby determine a second comparison signal;

a hysteretic voltage comparator for monitoring the supply voltage to thereby determine a third comparison signal; and

a logic circuit for generating a blanking signal according to the first, second and third comparison signals to blank the clock or the switching signal;

wherein the clock or the switching signal is blanked when the first comparison signal transits from a first state to a second state, and is released when the second comparison signal or the third comparison signal transits to a third state.

8. The apparatus of claim 7, wherein the logic circuit comprises:

an OR gate for generating a reset signal according to the second and third comparison signals; and

an RS latch for generating the blanking signal according to the first comparison signal and the reset signal.

9. The apparatus of claim 7, wherein the power switch is periodically switched when the second comparison signal transits to the third state.

10. The apparatus of claim 7, wherein the power switch is turned off when the first comparison signal transits from the first state to the second state, and is periodically switched when the second comparison signal transits to the third state.

11. The apparatus of claim 7, wherein the power switch is forced to be switched for a plurality of cycles when the third comparison signal transits to the third state.