Semiconductor memory device and method of operation

• US 20080310210A1
• Filed: 06/13/2007
• Published: 12/18/2008
• Est. Priority Date: 06/13/2007
• Status: Abandoned Application

• Current Assignee: Qimonda North America Corporation (Infineon Technologies AG)
• Original Assignee: Qimonda North America Corporation (Infineon Technologies AG)
• Inventors: Klostermann, Ulrich, Gogl, Dietmar
• Application Number:
  US11/818,196
• Publication Number:
  US 20080310210A1
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.

Claims

1. A memory cell comprising:

a storage element including a first terminal and a second terminal;

a select transistor including a first terminal, a second terminal and a control terminal, wherein a voltage at the control terminal affects a current flowing between the first terminal and the second terminal, the first terminal of the select transistor being coupled to the second terminal of the storage element;

a bit line coupled to the first terminal of the storage element;

a first word line coupled to the control terminal of the select transistor; and

a second word line coupled to the second terminal of the select transistor.

2. The memory cell of claim 1, wherein the memory cell is one memory cell in an array of memory cells, the memory cell being part of a row and column of the array, wherein the bit line is coupled to the first terminal of each memory cell in the column, the first word line is coupled to the control terminal of each memory cell in the row, and the second word line is coupled to the second terminal of each memory cell in the row.

3. A method of operating a memory cell, the method comprising:

enabling the memory cell, wherein the enabling comprises,

switching a first word line to a first voltage, the first word line coupled to a control terminal of the memory cell,

switching a second word line to a second voltage, the second word line coupled to a common terminal of the memory cell, and

applying a third voltage to a bit line, the bit line coupled to an output terminal of the memory cell, wherein the potential difference between the control terminal and common terminal is within a range of voltages that causes the output terminal to conduct a current which depends on an internal state of the memory cell; and

disabling the memory cell, wherein the disabling comprises,

switching the first word line to a fourth voltage,

switching the second word line to a fifth voltage, and

applying the third voltage to the bit line, wherein the potential difference between the control terminal and common terminal is within a range of voltages that substantially prevents the output terminal from conducting a current.

4. The method of claim 3, wherein the fourth voltage is substantially equal to the second voltage and wherein the fifth voltage is substantially equal to the third voltage.

5. The method of claim 3,

wherein the memory cell is disposed within a two dimensional array of memory cells comprising a plurality of rows and plurality of columns,

wherein each row comprises a separate first word line coupled to the control terminals of the memory elements in the row, and a separate second word line coupled to the common terminals of the memory elements in the row, and

wherein each column comprises a separate bit line coupled to the output terminals of the memory elements in the column.

6. The method of claim 3, wherein the memory cell comprises:

a memory element comprising a first terminal and a second terminal, the second terminal being coupled to the output terminal of the memory cell.;

a switch element comprising a control terminal, a common terminal, and an output terminal, wherein the control terminal is coupled to the control terminal of the memory cell, the common terminal is coupled to the common terminal of the memory cell, and the output terminal is coupled to the first terminal of the memory element

7. The method of claim 6, wherein the switch element comprises an MOS device.

8. The method of claim 6, wherein the resistance between the first terminal and second terminal of the memory element is programmable.

9. The method of claim 8, wherein the memory element comprises an MRAM memory element.

10. The method of claim 8, wherein the memory element comprises a CBRAM memory element.

11. The method of claim 8, wherein the memory element comprises a PCRAM memory element.

12. The method of claim 7, wherein the MOS device comprises an NMOS device and wherein the second and fourth voltages are ground, and the first voltage exceeds a threshold of the NMOS device.

13. The method of claim 5, wherein the enabling further comprises enabling a plurality of memory elements in one row of elements, and wherein the disabling further comprises disabling a plurality of memory elements in the rows of elements that have not been enabled.

14. The method of claim 3, the method further comprising writing information into the memory cell.

15. A semiconductor memory comprising:

an array of memory cells, the array comprising a first number of rows and a second number of columns, wherein each memory cell comprises a common node, a control node, and an output node;

a first number of first word lines, wherein each first word line is coupled to the control node of each memory cell in a particular row; and

a first number of second word lines, wherein each second word line is coupled to the common node of each memory cell in a particular row;

a second number of bit lines, wherein each bit line is coupled to the output node of each memory cell in a particular column, wherein a row of memory is read by applying a ground voltage on the second word line corresponding to the row to be read, applying a voltage which exceeds a read threshold on the first word line corresponding to the row to be read, applying a read voltage to each bit line, applying a voltage that does not exceed a read threshold on the first word lines that do not correspond to the rows to be read, and applying a voltage substantially equal to the voltage on the second word lines that do not correspond to the row to be read whereby a leakage current on the memory cells not being read is minimized.

16. The semiconductor memory of claim 15, wherein each memory cell comprises:

a switch device comprising a first terminal, and second terminal and a third terminal, wherein the resistance between the second terminal and the third terminal becomes lower when the voltage between the first terminal and the third terminal exceeds the read threshold, and wherein the first terminal is coupled to the control input of the memory cell, and the third terminal is coupled to the common node of the memory cell; and

a memory element comprising a first terminal and a second terminal, the first terminal coupled to the second terminal of the switch device and the second terminal coupled to the output of the memory cell, the memory cell having a resistance that depends on a programmed state.

17. The semiconductor memory of claim 16, wherein the switch device comprises a transistor.

18. The semiconductor memory of claim 17, wherein the transistor comprises an NMOS device.

19. The semiconductor memory of claim 16, wherein the memory element comprises an MRAM.

20. The semiconductor memory of claim 16, further comprising a second number of sense amplifiers, each sense amplifier coupled to one bit line, wherein the sense amplifier senses the current at the outputs of the memory cells coupled to a bit line.

21. A semiconductor device comprising,

a semiconductor body;

an array of memory cells disposed on the semiconductor body, the array comprising rows and columns;

a plurality of first word lines, each word line coupled to the memory cells along a row of the array of memory cells;

a plurality of second word lines, each word line coupled to the memory cells along a row of the array of memory cells;

a plurality of bit lines, each word line coupled to the memory cells along a column of the array of memory cells; and

a memory controller, wherein, when reading a row, the memory controller sets the second word line of the row to be read to ground and the first word line of the row to be read to a voltage exceeding a read threshold, and sets the second word lines of the rows not to be read to a first read voltage and the first word line of the row not to be read to a voltage not exceeding a read threshold, and the bit lines on the columns to be read to a second read voltage.

22. The semiconductor device of claim 21, further comprising a plurality of sense amplifiers, each sense amplifier coupled to a bit line, wherein the sense amplifier senses current drawn from each bit line.

23. The semiconductor device of claim 21, wherein each memory cell comprises a switch and a memory element, the switch and the memory element coupled in series, wherein the state of the element is represented by the impedance of the memory element.

24. The semiconductor device of claim 23, wherein the switch comprises a transistor.

25. The semiconductor device of claim 24, wherein the transistor comprises an NMOS device.

26. The semiconductor device of claim 23, wherein the memory element is an MRAM element.

27. The semiconductor device of claim 23, wherein the memory element is a PCRAM device.

28. The semiconductor device of claim 23, wherein the memory element is a CBRAM device.

29. The semiconductor device of claim 21, wherein the first and second read voltages are selected to minimize leakage current.