PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY

• US 20080310222A1
• Filed: 06/18/2007
• Published: 12/18/2008
• Est. Priority Date: 06/18/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,630,246 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.

Claims

1. A method for programming rate identification and control in a solid state memory comprising an array of memory cells having columns of memory cell coupled to bit lines, the method comprising:

identifying memory cells of the array that program at a faster rate than the remaining memory cells of the array; and

causing the memory cells that program at the faster rate to reach their respective programmed states at a substantially similar programming rate as the remaining memory cells by adjusting biasing of selected bit lines.

2. The method of claim 1 and further including storing an indication of a location of each identified memory cell that programs at the faster rate.

3. The method of claim 2 and further including storing an indication of a bit line bias voltage associated with the indication of the location.

4. The method of claim 1 wherein the programmed states are part of distributions of threshold voltages.

5. The method of claim 4 wherein each threshold voltage is represented by an analog voltage.

6. The method of claim 1 and further including reading an analog threshold voltage from each memory cell during programming and converting the analog threshold voltage to a digital representation of the analog threshold voltage.

7. A method for controlling programming rates of memory cells in a solid state memory comprising a plurality of bit lines coupled to columns of memory cells, the method comprising:

identifying a programming rate for each of the memory cells to determine faster programming memory cells and slower programming memory cells;

storing an indication of a location of each faster programming memory cell; and

changing the programming rate of the faster programming memory cells by increasing a selected bit line bias voltage, coupled to the faster programming memory cells, such that the bias voltage is greater than a bit line enable voltage.

8. The method of claim 7 and further including:

receiving a program command comprising a logical address; and

accessing the stored indications of the locations of each of the faster programming memory cells in memory to determine if the logical address matches any of the indications of the locations of the faster programming memory cells.

9. The method of claim 7 and further including storing an indication of the programming rate associated with each faster programming memory cell.

10. The method of claim 7 and further including storing an indication of the bit line bias voltage, associated with each faster programming memory cell, that provides a predetermined programming rate.

11. A method for controlling programming rates of memory cells in a non-volatile solid state memory comprising a plurality of bit line columns of memory cells, the method comprising:

determining a programming rate for each of the memory cells such that the memory cells are either faster programming memory cells or slower programming memory cells; and

programming, substantially simultaneously, a faster programming memory cell and a slower programming memory cell while adjusting the programming rate of the faster programming memory cell in response to biasing a selected bit line coupled to the faster programming memory cell with a voltage that is greater than an enable voltage such that the slower programming memory cell and the faster programming memory cell reach their respective programmed states substantially simultaneously.

12. The method of claim 11 and further including receiving a digital representation of a desired threshold voltage.

13. The method of claim 11 wherein the enable voltage is ground potential and the voltage is greater than ground potential and less than Vcc.

14. The method of claim 11 wherein determining the programming rate comprises:

applying a programming pulse to each of the memory cells; and

determining a change in threshold voltage for each memory cell such that memory cells with a greater change in threshold voltage than remaining memory cells are faster programming memory cells and the remaining memory cells are the slower programming memory cells.

15. The method of claim 14 wherein the threshold voltages are determined by reading an analog voltage that is indicative of the threshold voltage.

16. The method of claim 15 wherein the analog voltage is converted to a digital value that is indicative of a threshold voltage by a digital-to-analog conversion process.

17. A method for controlling programming rate of memory cells in a non-volatile solid state memory comprising a plurality bit lines, each bit line coupled to a column of memory cells, the method comprising:

reading a first threshold voltage prior to a first programming pulse for each of the memory cells;

applying the first programming pulse to each of the memory cells;

reading a second threshold voltage after the first programming pulse for each of the memory cells;

determining a difference between the first and second threshold voltages to find faster programming memory cells and slower programming memory cells wherein the faster programming memory cells have a greater difference between the first and second threshold voltages than the slower programming memory cells; and

biasing a selected bit line, coupled to each of the faster programming memory cells, with a voltage that is greater than an enable voltage and less than an inhibit voltage such that the programming rate of the faster programming memory cells is decreased.

18. The method of claim 17 and further comprising converting the first and second threshold voltages to digital signals indicative of the first and second threshold voltages.

19. The method of claim 17 wherein biasing comprises writing the voltage to a capacitor coupled to the selected bit line such that the capacitor holds the voltage on the selected bit line during programming.

20. A method for controlling programming of memory cells in a non-volatile solid state memory comprising a plurality of bit line columns and a plurality of word line rows, the method comprising:

biasing a selected word line coupled to the memory cells with a programming pulse;

reading an analog threshold voltage for each of the memory cells;

determining faster programming memory cells having an analog threshold voltage greater than a predetermined threshold and slower programming memory cells having an analog threshold voltage less than the predetermined threshold; and

biasing first selected bit lines coupled to the faster programming memory cells with a voltage greater than an enable voltage and less than an inhibit voltage and second selected bit lines coupled to the slower programming memory cells with the enable voltage such that each of the memory cells coupled to the selected word line that are being programmed reach their respective programmed state threshold voltage substantially simultaneously.

21. The method of claim 20 and further including receiving an analog representation of a desired threshold voltage for each of the memory cells to be programmed that are coupled to the selected word line.

22. A method for programming memory cells in a non-volatile, solid state memory organized in a plurality of bit line columns and a plurality of word line rows, the method comprising:

receiving a program command comprising a received memory cell address and a data value having a programmed state;

if the received memory cell address is equal to a stored memory cell address of a faster programming memory, reading stored bit line voltage data, associated with the stored memory cell address, from memory; and

biasing a selected bit line coupled to the received memory cell address in response to the stored bit line voltage data.

23. The method of claim 22 and further including biasing unselected bit lines with an inhibit voltage and remaining, selected bit lines with an enable voltage.

24. A solid state memory device, comprising:

an array of non-volatile memory cells having columns of memory cells coupled to bit lines and rows of memory cells coupled to word lines; and

circuitry for control and access of the array of non-volatile memory cells wherein the circuitry for control and access is adapted to control a rate of programming of the array of non-volatile memory cells by generating a selected bit line bias greater than an enable voltage and in response to a rate of change of a threshold voltage of each of the memory cells.

25. The solid state memory device of claim 24 wherein the circuitry for control and access is further adapted to read analog data signals from the memory cells being programmed and to generate digital threshold voltage signals indicative of the read analog data signals.

26. The solid state memory device of claim 24 and further including a biasing capacitor coupled to each bit line wherein the circuitry for control and access is further adapted to write the selected bit line bias to the biasing capacitor during a programming operation.

27. The solid state memory device of claim 24 wherein the circuitry for control and access of the array of non-volatile memory cells comprises circuitry to receive a digital data signal indicative of a programmed memory state and to convert the digital data signal to an analog data signal indicative of a threshold voltage of the programmed memory state.

28. The solid state memory device of claim 24 wherein the array of non-volatile memory cells is organized in a NAND architecture.

29. A method for identifying and controlling programming rate in a solid state memory having an array of memory cells, the method comprising:

identifying memory cells of the array that program at a faster rate than the remaining memory cells of the array; and

causing the memory cells that program at the faster rate to reach their respective programmed states substantially simultaneously with the remaining memory cells reaching their respective programmed states.

30. The method of claim 29 and further including storing an indication of a location of each identified memory cell that programs at the faster rate.