Memory with correlated resistance

• US 20080310228A1
• Filed: 06/15/2007
• Published: 12/18/2008
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Baker, R. Jacob
• Granted Patent: US 7,969,783 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices

Abstract

Methods, systems, and devices are disclosed, such as a method of operating a memory device. In certain embodiments, such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.

Claims

1. A method of operating a memory device, comprising:

writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.

2. The method of claim 1, wherein each of the plurality of data locations comprises a floating gate transistor.

3. The method of claim 2, wherein a source of each floating gate transistor is coupled to a drain of an adjacent floating gate transistor.

4. The method of claim 3, wherein writing comprises first writing to a floating gate transistor at the end of the series before writing to the other floating gate transistors.

5. The method of claim 4, wherein writing comprises writing to every floating gate transistor in a sequence based on the number of floating gate transistors between each floating gate transistor and the floating gate transistor at the end of the series.

6. The method of claim 1, wherein writing comprises:

adjusting a parameter of one of the data locations by an increment;

reading the value stored by the one of the data locations;

determining whether the value stored corresponds to a value to be written; and

if the value stored does not correspond to the value to be written, adjusting the parameter by another increment.

7. The method of claim 6, wherein the parameter is a charge on a floating gate transistor.

8. The method of claim 6, wherein reading comprises sensing a current through the one of the data locations with a delta-sigma modulator.

9. The method of claim 1, comprising erasing the plurality of data locations generally simultaneously.

10. The method of claim 1, comprising reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator.

11. The method of claim 10, wherein the value of a source-side resistance of the data location, when reading, is generally equal to a source-side resistance of the data location, when writing.

12. The method of claim 10, comprising transmitting data read from the data location to a processor of a computer system.

13. A system, comprising:

a plurality of floating gate transistors coupled in series source-to-drain; and

a controller configured to write to each of the plurality of floating gate transistors in sequence such that, for each of the plurality of floating gate transistors, source-side floating gate transistors are written to first.

14. The system of claim 13, wherein the controller is configured to write to each of the plurality of floating gate transistors by repeatedly incrementally adjusting a charge stored by each of the floating gate transistors and reading a data value stored by each of the floating gate transistors until the data value is generally equal to a pre-determined value.

15. The system of claim 13, wherein each plurality floating gate transistors is coupled to a quantizing circuit that comprises a delta-sigma modulator and a digital filter.

16. The system of claim 15, wherein the delta-sigma modulator comprises:

a comparator; and

a current switch controlled by an output of the comparator, wherein the current switch is configured to open and close a current path through the memory cell.

17. The system of claim 15, wherein the digital filter comprises a counter.

18. A method of operating an integrated semiconductor device, comprising:

erasing a plurality of floating gate transistors coupled to each other in a series source-to-drain;

writing to each of the plurality of floating gate transistors one at a time, in sequence, starting with a floating gate transistor at an end of the series and finishing with a floating gate transistor at the other end of the series.

19. The method of claim 18, wherein the plurality of floating gate transistors are erased generally simultaneously.

20. The method of claim 18, comprising reading from one of the plurality of floating gate transistors, wherein reading is performed before any of the floating gate transistors is written to again.

21. The method of claim 18, wherein writing comprises incrementally adjusting a charge on each of the floating gate transistors and sensing whether the charge corresponds to a desired value.

22. The method of claim 18, comprising reading from one of the plurality of floating gate transistors with a delta-sigma modulator.

23. The method of claim 22, wherein reading comprises transmitting a bit-stream from the delta-sigma modulator to a counter.

24. The method of claim 22, wherein reading comprises truncating a least significant bit from an output of the counter.