PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS

• US 20080310246A1
• Filed: 06/12/2007
• Published: 12/18/2008
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Houle, Robert Maurice, Batson, Kevin A., Joshi, Rajiv V.
• Granted Patent: US 7,701,801 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Claims

1. A local on-chip programmable pulsewidth and delay generating circuit, comprising:

a clock generation circuit configured to receive a global clock signal and output a local clock signal, the clock generation circuit including a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay;

the leading edge delay being generated by a leading edge delay circuit;

the trailing edge delay being generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse;

the trailing edge delay circuit including a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

2. The circuit as recited in claim 1, wherein the delay chain includes NAND gates configured to introduce delay elements in accordance with the control bits.

3. The circuit as recited in claim 1, wherein the control bits are output from a wordline address scan using word line decode latches.

4. The circuit as recited in claim 1, wherein the leading edge delay circuit provides a plurality of programmable delay settings for delaying the pulse.

5. The circuit as recited in claim 1, wherein the trailing edge delay circuit includes a fine control delay element which provides a plurality of programmable delay settings.

6. The circuit as recited in claim 1, further comprising a no chop circuit configured to restore an original pulsewidth in accordance with a control bit.

7. The circuit as recited in claim 1, further comprising an address encoder configured to activate the local clock in accordance with address input signals.

8. The circuit as recited in claim 1, wherein the local clock generates wordline pulses.

9. The circuit as recited in claim 1, wherein the wordline pulses include the local clock signal plus a delay to improve read/write margin.

10. The circuit as recited in claim 1, wherein the generating circuit is included in one or more individual clock blocks where the clock blocks include at least one of a word clock block, a bit clock block, a read/write clock block, wordline generation, and global reset generation.

11. The circuit as recited in claim 1, further comprising an on-chip stress circuit configured to stress memory cells by incrementally adjusting word line pulse width in accordance with the on-chip programmable pulsewidth and delay generating circuit.

12. A method for local on-chip programmable pulsewidth and delay generation, comprising:

outputting a local clock signal from a global clock signal by pulse shaping a pulse of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay, wherein shaping the pulse includes;

generating the leading edge delay includes providing a plurality of programmable delay settings for delaying the pulse; and

generating a trailing edge delay includes delaying the trailing edge using a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

13. The method as recited in claim 12, wherein the delay chain includes NAND gates configured to introduce delay elements in accordance with the control bits and further comprising controlling an amount of delay in accordance with control bits output from a wordline address scan using word line decode latches.

14. The method as recited in claim 12, wherein generating the trailing edge delay includes employing a fine control delay element which provides a plurality of programmable delay settings.

15. The method as recited in claim 12, further comprising restoring an original pulsewidth by employing a no chop circuit activated in accordance with a control bit.

16. The method as recited in claim 12, further comprising generating wordline pulses from the local clock signal.

17. The method as recited in claim 12, further comprising stressing memory cells by incrementally adjusting word line pulse width in accordance with the on-chip programmable pulsewidth and delay generation.

18. A memory circuit, comprising:

a memory array including memory cells;

a local wordline configured to address a row of memory cells; and

a driver coupled to the local wordline, the driver being responsive to a control signal such that the local wordline is turned on locally only for the memory cells being written to by write bitlines to reduce charge leakage due to half-selection of the memory cells.

19. The memory circuit as recited in claim 18, wherein the memory array includes separate write wordline and read wordlines.

20. The circuit as recited in claim 18, wherein the memory cells include eight transistors, wherein two transistors are configured for read operations only.

21. An evaluation circuit for bitline operations, comprising:

a pair of local bitlines selectively connected to a plurality of memory cells to provide access to the plurality of memory cells;

a control circuit configured to enable an operation for outputting data from the memory cells; and

a PFET driver being enabled by a respective local bitline to drive a global bitline to a supply value in accordance with a low value stored in a respective memory cell.

22. The circuit as recited in claim 21, wherein the supply value is a supply voltage of a memory array (VCS).

23. The circuit as recited in claim 21, wherein the supply value is higher than a supply voltage of other transistors in the circuit.

24. The circuit as recited in claim 21, wherein the global bitlines includes separate write and read bitlines.

25. An evaluation circuit for bitline operations, comprising:

a logic gate having inputs selectively coupled to a pair of local bitlines to compare states between the bitlines; and

a keeper circuit including a plurality of transistors having gates connected to a conditional keeper control signal and an output of the logic gate such that a state of the local bitlines is evaluated by the logic gate and conditioned by the keeper circuit in accordance with feedback from the logic gate.

26. The circuit as recited in claim 25, wherein the conditional keeper control signal includes an always on condition, an always off condition and a delayed on condition.

27. The circuit as recited in claim 25, wherein the logic gate includes a NAND gate.

28. The circuit as recited in claim 25, further comprising a precharge circuit configured to precharge input nodes of the logic gate during a precharge period.

29. The circuit as recited in claim 25, wherein the conditional keeper control signal is based on a dummy global bitline signal to delay turn on of the keeper circuit.

30. The circuit as recited in claim 25, further comprising a transistor having a gate coupled to the output of the logic gate to provide access to a global bitline.

31. The circuit as recited in claim 30, wherein a plurality of evaluation circuits are ORed to the global bitline.

32. A global evaluation circuit for bitline operations, comprising:

a pair of global bitlines selectively connected to a plurality of local evaluation circuits to permit access to local bitlines;

a control circuit configured to control access to the global bitlines for operations between the local evaluation circuits and output latches; and

a predischarge circuit responsive to a global reset signal and configured to selectively discharge the global bitlines, the global reset signal being derived from one of a wordline clock pulse and an independently controlled by a separate clock block.

33. The circuit as recited in claim 32, wherein the separate clock block includes a clock generation circuit configured to receive a global clock signal and output a local clock signal, the clock generation circuit including a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay;

the leading edge delay being generated by a leading edge delay circuit;

the trailing edge delay being generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse;

the trailing edge delay circuit including a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.