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PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS

  • US 20080310246A1
  • Filed: 06/12/2007
  • Published: 12/18/2008
  • Est. Priority Date: 06/12/2007
  • Status: Active Grant
First Claim
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1. A local on-chip programmable pulsewidth and delay generating circuit, comprising:

  • a clock generation circuit configured to receive a global clock signal and output a local clock signal, the clock generation circuit including a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay;

    the leading edge delay being generated by a leading edge delay circuit;

    the trailing edge delay being generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse;

    the trailing edge delay circuit including a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

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