ERROR CONTROL APPARATUS

• US 20080310297A1
• Filed: 08/22/2008
• Published: 12/18/2008
• Est. Priority Date: 02/24/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Nakagawa, Satoshi, MURAKAMI, Hiroshi, Kusano, Yoshihiro, Sugizaki, Gou
• Granted Patent: US 8,264,948 B2
• Time in Patent Office: Days
• US Class Current: 370/216
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 2001/0097 Relays

Abstract

A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

Claims

1. An error control apparatus provided in an interconnection device for interconnecting a plurality of information processing modules, comprising:

an error detection unit for detecting an error in an input packet;

a completion data generation unit for generating completion data in accordance with a position at which an error is detected in the input packet; and

an output unit for outputting a completion packet in which the completion data is provided in place of a data unit involving the detected error and a subsequent data unit.

2. The error control apparatus according to claim 1, wherein

the input packet includes information representing the number of data units contained in the input packet, and

the completion data generation unit counts the number of data units involving the error detected by the error detection unit and subsequent data unit, and generates as many units of completion data as the counted number.

3. The error control apparatus according to claim 1, wherein

the input packet contains a data unit to which an error correcting code is added, and

the completion data generation unit generates completion data to which an error correcting code is added.

4. The error control apparatus according to claim 1, further comprising a discarding unit for discarding, after an error is detected in a packet sent out from a first information processing module among the plurality of information processing modules, all the packets received from the first information processing module.

5. The error control apparatus according to claim 1, further comprising a discarding unit for discarding, after an error is detected in a packet sent out from a first information processing module among the plurality of information processing modules, a packet other than a prescribed type of packet among packets received from the first information processing module.

6. The error control apparatus according to claim 1, further comprising a reporting unit for reporting, when an error is detected in a packet sent out from a first information processing module among the plurality of information processing modules, an occurrence of an error to the first information processing module.

7. The error control apparatus according to claim 1, further comprising a partitioning unit for classifying the plurality of information processing modules into two or more groups, wherein

the error detection unit determines that an error has occurred when a destination of a packet sent out from an information processing module belonging to a first group includes an information processing module belonging to a second group.

8. An error control apparatus provided in an interconnection device for interconnecting a plurality of information processing modules, comprising:

a holding unit for temporarily holding an input packet;

an error detection unit for detecting an error in the input packet; and

an output unit for reading a packet from the holding unit and outputting the read packet to a destination information processing module only when no error is detected in all area of the input packet.

9. A method of controlling an error in an interconnection device for interconnecting a plurality of information processing modules, comprising:

monitoring an error in an input packet;

generating completion data in accordance with a position at which an error is detected in the input packet; and

outputting a completion packet in which the completion data is provided in place of a data unit involving the detected error and a subsequent data unit.