Input/output circuit

• US 20080310569A1
• Filed: 05/30/2008
• Published: 12/18/2008
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takeuchi, Masahiro
• Granted Patent: US 8,290,028 B2
• Time in Patent Office: Days
• US Class Current: 375/357
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Disclosed is a SERDES circuit including a clock and data recovery circuit that allows operational margin in temporal and voltage directions to be measured, using a phase offset signal and a threshold voltage control signal, a pre-emphasis driver circuit and an equalizer circuit in order to reduce ISI on a transmission line, and an optimization control circuit for controlling the overall circuit. The optimization control circuit controls an equalizer control signal that is for adjusting characteristics of the equalizer circuit and a driver control signal that is for adjusting characteristics of the pre-emphasis driver circuit and sets the equalizer control signal and driver control signal so that the operational margin of the clock and data recovery circuit is maximized.

Claims

1. An input/output circuit comprising:

a clock and data recovery circuit that extracts clock and data from input data;

said clock and data recovery circuit capable of measuring operational margin thereof in a temporal direction and in a voltage direction; and

an optimization control circuit that performs control so that characteristic of a pre-emphasis driver circuit that pre-emphasizes and drives output data and/or characteristic of an equalizer circuit that equalizes the input data, are optimized, based on a measurement result of the operational margin of said clock and data recovery circuit.

2. The input/output circuit according to claim 1, comprising:

a transmit circuit including said pre-emphasis driver circuit; and

a receive circuit including;

said equalizer circuit;

said clock and data recovery circuit receiving the input data equalized by said equalizer circuit; and

said optimization control circuit;

wherein said optimization control circuit performs optimization of the characteristics of said pre-emphasis driver circuit and said equalizer circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

3. The input/output circuit according to claim 1, comprising:

a transmit circuit including said pre-emphasis driver circuit; and

a receive circuit including said clock and data recovery circuit and said optimization control circuit;

wherein said optimization control circuit performs optimization of the characteristic of said pre-emphasis driver circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

4. The input/output circuit according to claim 1, comprising:

a receive circuit including;

said equalizer circuit;

said clock and data recovery circuit receiving the input data equalized by said equalizer circuit; and

said optimization control circuit;

wherein said optimization control circuit performs optimization of the characteristic of said equalizer circuit, based on the measurement result of the operational margin of said clock and data recovery circuit.

5. The input/output circuit according to claim 1, comprising:

a parallel-to-serial converting circuit that receives parallel data, converts the parallel data into serial data, and supplies the serial data to said pre-emphasis driver circuit; and

a selection circuit that selects, as the parallel data supplied to said parallel-to-serial converting circuit, either one of parallel data to be transmitted during a normal operation and an opposing driver control signal for controlling characteristic of a pre-emphasis driver circuit provided in an input/output circuit of an opposing device, said opposing driver control signal being generated by said optimization control circuit.

6. The input/output circuit according to claim 5, comprising:

a serial-to-parallel data converting circuit that converts serial data output from said clock and data recovery circuit into parallel data;

wherein said optimization control circuit monitors the parallel data output from said serial-to-parallel data converting circuit and controls said pre-emphasis circuit of an own device when the opposing driver control signal is received.

7. The input/output circuit according to claim 1, wherein said clock and data recovery circuit comprises:

a data sampling circuit that samples the input data responsive to a clock signal;

a phase comparator that receives the input data sampled by said data sampling circuit and detects a phase relationship between the clock and the sampled input data;

a phase controller that outputs a phase control signal based on a result of phase comparison by said phase comparator; and

a phase interpolator that generates a clock signal having a phase interpolated based on the phase control signal;

the clock signal from said phase interpolator being supplied to said data sampling circuit, thereby forming a loop;

said phase controller generating another phase control signal different from the phase control signal;

said clock and data recovery circuit further comprising;

another phase interpolator that receives said another phase control signal output from said phase controller and generates another clock signal phase-interpolated based on said another phase control signal;

a threshold voltage generator that generates a threshold voltage;

another data sampling circuit that samples the input data responsive to said another clock signal from said another phase interpolator and the threshold voltage; and

a comparison circuit that compares the data sampled by said data sampling circuit and the data sampled by said another data sampling circuit;

a result of the comparison by said comparison circuit being supplied to said optimization control circuit as an error detection result.

8. The input/output circuit according to claim 7, wherein

said optimization control circuit supplies to said phase controller a phase offset signal for adding a phase offset between the phase control signal and the other phase control signal generated by said phase controller, thereby variably controlling the phase offset;

said optimization control circuit supplies to said threshold voltage generator a threshold voltage control signal that controls the threshold voltage to be generated by said threshold voltage generator, thereby variably controlling the threshold voltage; and

the measurement of the operational margin of said clock and data recovery circuit in the temporal and voltage directions is carried out by checking whether said another data sampling circuit could correctly sample the data based on the error detection result from said comparison circuit.

9. The input/output circuit according to claim 1, wherein the optimization by said optimization control circuit is executed at power-on.

10. The input/output circuit according to claim 1, wherein the optimization by said optimization control circuit is executed at a first time of the power-on, a result of the optimization is stored in a non-volatile storage device, and the result stored in said storage device is used at subsequent times of the power on.

11. The input/output circuit according to claim 1, wherein the optimization by said optimization control circuit is performed at a time of a normal data transmitting operation as well;

and

data transmission is performed with the characteristics of said pre-emphasis driver circuit and/or said equalizer circuit kept to be optimal with respect to a change in the characteristics of said pre-emphasis driver circuit and/or said equalizer circuit.

12. An interface circuit that converts parallel data, for serial transmission and converts received serially transmitted data into parallel data, including:

the input/output circuit as set forth in claim 1.

13. A semiconductor device including the input/output circuit as set forth in claim 1.