RECTIFIER CIRCUIT AND RFID TAG

• US 20080311850A1
• Filed: 08/05/2008
• Published: 12/18/2008
• Est. Priority Date: 11/09/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ootaka, Shoji, Umeda, Toshiyuki
• Granted Patent: US 7,853,236 B2
• Time in Patent Office: Days
• US Class Current: 455/41.1
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0702 the arrangement including a battery
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A rectifier circuit includes a first MOS transistor; a first capacitor connected between a gate and a source of the first MOS transistor; a first switching circuit for supplying a bias voltage to the first capacitor in response to a control signal; a second MOS transistor whose drain is connected to the source of the first MOS transistor; a second capacitor connected between a gate and a source of the second MOS transistor; and a second switching circuit for supplying the bias voltage to the second capacitor in response to the control signal. The rectifier circuit also includes a third MOS transistor for imitating the first MOS transistor; a third capacitor for imitating the first capacitor; a dummy switching circuit for supplying the bias voltage to the third capacitor in response to the control signal; and a generating circuit for generating the control signal based on a potential of the third capacitor.

Claims

1. A rectifier circuit comprising:

a first MOS transistor;

a first capacitor configured to connect between a gate and a source of the first MOS transistor;

a first switching circuit configured to supply a bias voltage to the first capacitor in response to a control signal;

a second MOS transistor whose drain is connected to the source of the first MOS transistor;

a second capacitor configured to connect between a gate and a source of the second MOS transistor;

a second switching circuit configured to supply the bias voltage to the second capacitor in response to the control signal;

a third MOS transistor configured to imitate the first MOS transistor;

a third capacitor configured to imitate the first capacitor;

a fourth capacitor connected between a drain of the first MOS transistor and the source of the second MOS transistor, a direct current being supplied through the fourth capacitor with respect to an alternating current supplied to the source of the first MOS transistor;

a dummy switching circuit configured to supply the bias voltage to the third capacitor in response to the control signal; and

a generating circuit configured to generate the control signal based on a potential of the third capacitor.

2. The rectifier circuit according to claim 1, further comprising a bias voltage source configured to include a fourth MOS transistor, and generates the bias voltage from a gate-to-source voltage of the fourth MOS transistor.

3. The rectifier circuit according to claim 1, further comprising a reference voltage source configured to generate a reference voltage lower than the bias voltage,

wherein the bias setting circuit generates the control signal based on a result of comparison of the reference voltage and the potential of the third capacitor.

4. The rectifier circuit according to claim 3, wherein the reference voltage source includes a fifth MOS transistor, and generates the reference voltage from a gate-to-source voltage of the fifth MOS transistor.

5. The rectifier circuit according to claim 1, wherein the bias setting circuit supplies the bias voltage to the third capacitor in response to a reset signal for initializing a voltage across the third capacitor.

6. The rectifier circuit according to claim 5, wherein the rectifier circuit supplies the bias voltage to the first capacitor in response to the reset signal.

7. The rectifier circuit according to claim 5, further comprising a power detector circuit configured to generate the reset signal in response to detection of a power supply voltage for the rectifier circuit.

8. The rectifier circuit according to claim 1, wherein a source of the third MOS transistor is grounded.

9. The rectifier circuit according to claim 1, wherein a source of the third MOS transistor has a potential between a power supply potential and the ground potential.

10. The rectifier circuit according to claim 1, further comprising:

a logic circuit configured to generate a logic signal based on the control signal and a signal delayed by a predetermined time to the control signal; and

an inverter circuit configured to supply one of the ground potential and a potential between a power supply potential and the ground potential to a source of the third MOS transistor in response to the logic signal.

11. The rectifier circuit according to claim 10, wherein the predetermined time is a time required to have supplied the bias voltage to the third capacitor through the dummy switching circuit.

12. The rectifier circuit according to claim 1, wherein the bias setting circuit further includes a current supply circuit for supplying a predetermined current to one end of the third capacitor, and generates the control signal based on a potential of the third capacitor increased with the predetermined current flowing therein.

13. The rectifier circuit according to claim 12, wherein the first switching circuit includes a MOS transistor for supplying the bias voltage to the first capacitor in response to the control signal,

the second switching circuit includes a MOS transistor for supplying the bias voltage to the second capacitor in response to the control signal, and

the predetermined current corresponds to a leakage current of the MOS transistor in the first switching circuit.

14. The rectifier circuit according to claim 12, wherein the bias setting circuit further includes a fourth MOS transistor imitating the first transistor, a fourth capacitor imitating the first capacitor, and a second dummy switching circuit for supplying the bias voltage to the fourth capacitor in response to the control signal, and generates the control signal based on potentials of the third capacitor and the fourth capacitor.

15. The rectifier circuit according to claim 1, wherein the switching circuit includes a fifth MOS transistor for supplying the bias voltage to the first capacitor in response to the control signal, and

the dummy switching circuit includes a sixth MOS transistor imitating the fifth MOS transistor and being larger in scale than the fifth MOS transistor.

16. A radio frequency identification tag comprising:

an antenna;

a first MOS transistor;

a first capacitor configured to connect between a gate and a source of the first MOS transistor;

a first switching circuit configured to supply a bias voltage to the first capacitor in response to a control signal;

a second MOS transistor whose drain is connected to the source of the first MOS transistor;

a second capacitor configured to connect between a gate and a source of the second MOS transistor;

a second switching circuit configured to supply the bias voltage to the second capacitor in response to the control signal;

a third MOS transistor configured to imitate the first MOS transistor;

a third capacitor configured to imitate the first capacitor;

a fourth capacitor connected between a drain of the first MOS transistor and the source of the second MOS transistor;

a dummy switching circuit configured to supply the bias voltage to the third capacitor in response to the control signal;

a generating unit configured to generate the control signal based on a potential of the third capacitor;

a battery configured to be charged with a direct current supplied through the fourth capacitor with respect to an alternating current supplied to the source of the first MOS transistor; and

a control circuit configured to transmit tag identification information via the antenna based on the direct current.

17. The radio frequency identification tag according to the claim 16, further comprising a sensor,

wherein the control circuit transmits a signal output from the sensor via the antenna.

18. A radio frequency identification tag comprising:

an antenna;

a first MOS transistor;

a first capacitor configured to connect between a gate and a source of the first MOS transistor;

a first switching circuit configured to supply a bias voltage to the first capacitor in response to a control signal;

a second MOS transistor whose drain is connected to the source of the first MOS transistor;

a second capacitor configured to connect between a gate and a source of the second MOS transistor;

a second switching circuit configured to supply the bias voltage to the second capacitor in response to the control signal;

a third MOS transistor configured to imitate the first MOS transistor;

a third capacitor configured to imitate the first capacitor;

a fourth capacitor connected between a drain of the first MOS transistor and the source of the second MOS transistor;

a dummy switching circuit configured to supply the bias voltage to the third capacitor in response to the control signal;

a generating unit configured to generate the control signal based on a potential of the third capacitor;

a supplying unit configured to supply the bias voltage to the third capacitor in response to a reset signal;

a battery configured to be charged with a direct current supplied through the fourth capacitor with respect to an alternating current supplied to the source of the first MOS transistor; and

a control circuit configured to transmit tag identification information via the antenna based on the direct current, and outputs the reset signal when the control circuit enters suspend state from running state.

19. The radio frequency identification tag according to the claim 18, further comprising a sensor,

wherein the control circuit transmits a signal output from the sensor via the antenna.