INTEGRATED GALVANIC ISOLATOR USING WIRELESS TRANSMISSION

• US 20080311862A1
• Filed: 05/12/2008
• Published: 12/18/2008
• Est. Priority Date: 05/11/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Smerzi, Santo Alessandro, Palmisano, Giuseppe, Girlando, Giovanni, Spina, Nunzio
• Granted Patent: US 8,364,195 B2
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/525 between emitting and receiving antennas
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation

Abstract

An embodiment of a wireless galvanic isolator device is formed by a transmitter circuit, a receiver circuit, and a wireless coupling structure, arranged between the transmitter circuit and the receiver circuit. The wireless coupling structure is formed by a pair of antennas each arranged on an own die and integrated together with the respective transmitter and receiver circuit. The two dice may be arranged adjacent to each other in a planar configuration or arranged on top of each other and bonded together.

Claims

1. A wireless galvanic-isolator device comprising a transmitter circuit, a receiver circuit, and wireless coupling means arranged between said transmitter circuit and said receiver circuit, wherein said wireless coupling means comprise an antenna.

2. The device according to claim 1, wherein the antenna is formed by a transmitting antenna and a receiving antenna;

said transmitter circuit and said transmitting antenna being integrated in a first die;

said receiver circuit and said receiving antenna being integrated in a second die;

said first and second dice being encapsulated in a single package.

3. The device according to claim 2, wherein the first and second dice are arranged on top of one another and galvanically isolated from one another by an isolating layer, arranged between said first and second dice.

4. The device according to claim 3, wherein said first and second dice each comprise a semiconductor material substrate and a passivation region, the semiconductor material substrates of said first and second dice integrating, respectively, said transmitter circuit and said receiver circuit, said transmitting antenna and receiving antenna being formed in a top metal layer within the passivation region of said first die and of said second die, respectively.

5. The device according to the claim 4, wherein an isolating layer is arranged between said passivation region of said second die and said semiconductor material substrate of said first die.

6. The device according to claim 2, wherein the first and second dice are arranged adjacent to each other and lie on a same plane.

7. The device according to claim 6, wherein said first and second dice are carried by separate supporting structures and each comprise an active area integrating said transmitter circuit and, respectively, said receiver circuit;

said transmitting antenna and said receiving antenna surrounding a respective active area.

8. The device according to claim 1, wherein said transmitter circuit comprises a data input receiving an input signal and an on-off modulation stage, connected between said data input and said transmitting antenna;

and said receiver circuit comprises a data output and a demodulation stage, connected between said receiving antenna and said data output.

9. The device according to claim 8, wherein said input signal has a first logic level and a second logic level, and said on-off modulation stage generates a radiofrequency signal having a first amplitude and a second amplitude associated, respectively, with said first and said second logic levels of said input signal.

10. The device according to claim 9, wherein said input signal comprises a plurality of channel signals, and said on-off modulation stage comprises a parallel-to-serial converter, which receives said plurality of channel signals and a first clock signal and has an output connected to an RF oscillator;

said RF oscillator further receiving said first transmission clock signal and having an output connected to a first buffer circuit;

said first buffer circuit having an output connected to said transmitting antenna.

11. The device according to claim 10, wherein said demodulation stage comprises a mixer stage connected to said receiving antenna and having an output connected to a lowpass filter;

said lowpass filter having an output connected to a first trigger circuit and a second trigger circuit;

said first trigger circuit having an own threshold voltage, correlated to the first amplitude of the radiofrequency signal, and said second trigger circuit having an own threshold voltage correlated to the second amplitude of the radiofrequency signal, said first and second trigger circuit being connected to said data output through a serial-to-parallel converter.

12. The device according to claim 11, wherein said second amplitude is smaller than said first amplitude and said second trigger circuit outputs a second clock signal supplied to said serial-to-parallel converter.

13. The device according to claim 11, wherein said first trigger circuit and said second trigger circuit have respective outputs connected to a data input and a timing input of a synchronization stage, which is arranged between said first and said second trigger circuits and said parallel-to-serial converter.

14. The device according to claim 1, wherein said transmitting antenna and said receiving antenna operate in near-field conditions.

15. The device according to claim 1, wherein said transmitting antenna and said receiving antenna operate in far-field conditions.

16. The device according to claim 1, wherein said transmitting antenna and said receiving antenna are chosen between dipole antennas, bent-dipole antennas, loop antennas.

17. The device according to claim 1, wherein a protection circuit is connected to an intermediate node between said receiving antenna and said receiver circuit, said protection circuit having current-subtraction means increasing rejection of the receiver circuit to common-mode noise.

18. An integrated circuit, comprising:

a first die;

a transmitter disposed on the first die;

a transmit antenna disposed on the first die and coupled to the transmitter;

a second die;

a receiver disposed on the second die; and

a receive antenna disposed on the second die.

19. The integrated circuit of claim 18, further comprising:

a package; and

wherein the first and second dies are disposed within the package.

20. The integrated circuit of claim 18 wherein one of the first and second dies is disposed over the other of the first and second dies.

21. The integrated circuit of claim 18 wherein the first die is disposed adjacent to the second die.

22. The integrated circuit of claim 18 wherein the transmit antenna has substantially the same shape as the receive antenna.

23. The integrated circuit of claim 18 wherein the transmit and receive antennas are each substantially planar.

24. The integrated circuit of claim 18 wherein:

the transmit antenna has a transmit frequency band in which the gain of the transmit antenna ranges from a maximum transmit gain to a lower transmit gain that is an amount less than the maximum transmit gain; and

the receive antenna has a receive frequency band in which the gain of the receive antenna ranges from a maximum receive gain to a lower receive gain that is substantially the amount less than the maximum receive gain, the receive frequency band overlapping the transmit frequency band.

25. The integrated circuit of claim 18 wherein:

the transmit antenna has a transmit frequency band in which the gain of the transmit antenna ranges from a maximum transmit gain to a lower transmit gain that is an amount less than the maximum transmit gain; and

the receive antenna has a receive frequency band in which the gain of the receive antenna ranges from a maximum receive gain to a lower receive gain that is substantially the amount less than the maximum receive gain, the receive frequency band being substantially the same as the transmit frequency band.

26. The integrated circuit of claim 18 wherein the second integrated circuit comprises a common-mode-rejection circuit coupled to the receiver and operable to increase a common-mode-rejection ratio of the receiver.

27. The integrated circuit of claim 18 wherein the first die is spaced from the second die.

28. A system, comprising:

a first integrated circuit, comprising

a first die,

a transmitter disposed on the first die,

a transmit antenna disposed on the first die and coupled to the transmitter,

a second die,

a receiver disposed on the second die, and

a receive antenna disposed on the second die; and

a second integrated circuit coupled to the first integrated circuit.

29. The system of claim 28 wherein the second integrated circuit comprises a controller.

30. The system of claim 28 wherein the second integrated circuit is disposed on one of the first and second dies.

31. The system of claim 28 wherein the second integrated circuit is disposed on a third die.

32. The system of claim 28 wherein:

the first integrated circuit comprises a first package within which the first and second dies are disposed; and

the second integrated circuit comprises

a second package, and

a third die disposed within the second package.

33. The system of claim 28, further comprising:

a package;

wherein the first and second dies of the first integrated circuit are disposed within the package; and

the second integrated circuit comprises a third die disposed within the package.

34. A method, comprising:

generating a signal on a first die;

transmitting the signal via a transmit antenna disposed on the first die; and

receiving the transmitted signal with a receive antenna disposed on a second die.

35. The method of claim 34 wherein transmitting the signal comprises transmitting the signal within a package enclosing the first and second dies.

36. The method of claim 34, further comprising:

generating a common-mode-rejection compensating current; and

coupling the compensating current to the receive antenna.

37. The method of claim 34 wherein transmitting the signal comprises transmitting the signal from the transmit antenna, through at least one of the first and second dies, to the receive antenna.

38. The method of claim 34 wherein transmitting the signal comprises transmitting the signal from the transmit antenna, through a region between the first and second dies, to the receive antenna.