Input/output multiplexer bus

• US 20080312857A1
• Filed: 02/21/2007
• Published: 12/18/2008
• Est. Priority Date: 03/27/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sequine, Dennis R.
• Granted Patent: US 8,067,948 B2
• Time in Patent Office: Days
• US Class Current: 702/65
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G01R 27/26 Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/2829 Testing of circuits in sensor or actuator systems testing of apparatus for measuring electric or magnetic variables G01R35/00; testing of indicating or recording apparatus G01D; in airbag systems B60R21/0173; checking gas analysers G01N33/007; monitoring or fail-safe circuits for electromagnets H01F7/1844
• CPC Class Codes: G01R 31/64 Testing of capacitors

Abstract

An input/output (“I/O”) system includes a plurality of input/output (“I/O”) ports, measurement circuitry, and an I/O multiplexer bus. The measurement circuitry is coupled to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports. The I/O multiplexer bus is coupled between the I/O ports and the measurement circuitry. The I/O multiplexer bus is programmable to selectively couple the measurement circuitry to any of the I/O ports.

Claims

1. An apparatus, comprising:

a plurality of input/output (“

I/O”

) ports;

measurement circuitry to measure one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O ports; and

a I/O multiplexer bus coupled between the I/O ports and the measurement circuitry, the I/O multiplexer bus programmable to selectively couple the measurement circuitry to any of the I/O ports.

2. The apparatus of claim 1, wherein the I/O multiplexer bus comprises:

a bus line coupled to the measurement circuitry;

a plurality of bus line switches, each coupled between one of the I/O ports and the bus line; and

switching logic coupled to the bus line switches to control the bus line switches.

3. The apparatus of claim 2, further comprising a current source coupled to the bus line to drive a current through the bus line, wherein the switching logic is coupled to selectively drive the current through one or more of the I/O ports.

4. The apparatus of claim 3, wherein the measurement circuit comprises capacitance sensing circuitry to measure a variable capacitance of the one or more devices to be externally coupled to the one or more of the I/O ports.

5. The apparatus of claim 4, wherein the capacitance sensing circuitry comprises:

a comparator having a first input coupled to the bus line and a second input coupled to receive a reference voltage;

measurement logic coupled to receive an output from the comparator, the measurement logic to measure at least one of a duty cycle, a frequency, or a period of the output from the comparator;

a discharge switch coupled to selectively discharge the bus line; and

discharge logic coupled to receive the output from the comparator and to control the discharge switch in response to the output from the comparator.

6. The apparatus of claim 2, further comprising a voltage source, and wherein the I/O multiplexer bus further comprises:

a voltage line coupled to the voltage source; and

a plurality of voltage line switches, each coupled between the voltage line and one of the I/O ports, wherein the switching logic is further coupled to selectively couple the voltage source to any of the I/O ports via control of the voltage line switches.

7. The apparatus of claim 2, wherein the switching logic comprises:

a multi-bit register to store a multi-bit value, wherein the bus line switches are controlled responsive to the multi-bit value; and

a processor coupled to the multi-bit register to program the multi-bit register with the multi-bit value.

8. The apparatus of claim 7, wherein the switching logic further comprises:

a clock source to generate a clock signal; and

decoder logic coupled to the multi-bit register, the clock source, and the bus line switches, the decoder logic coupled to switch a selected one or more of the bus line switches based on the multi-bit value at a frequency based on the clock signal.

9. The apparatus of claim 2, further comprising a plurality of capacitance sense buttons of a capacitance sense interface, each of the capacitance sense buttons coupled externally to one of the I/O ports, wherein the decoder logic is coupled to time share the measurement circuitry on the I/O multiplexer bus to sequentially monitor a capacitance of each of the capacitance sense buttons.

10. An apparatus, comprising:

a plurality of input/output (“

I/O”

) means for conveying analog signals into and out of an integrated circuit;

measurement means for measuring one or more electrical properties of one or more devices to be externally coupled to one or more of the I/O means; and

means for time-sharing the measurement means across the plurality of I/O means, wherein the means for time-sharing is programmable to selectively individually couple the measurement means to any of the I/O means.

11. The apparatus of claim 10, wherein the means for time-sharing comprises:

a bus line coupled to the measurement means;

a plurality of bus line switches, each coupled between one of the I/O means and the bus line; and

means for controlling the bus line switches.

12. The apparatus of claim 11, further comprising a means for generating a current coupled to the bus line to drive the current through the bus line and wherein the measurement means comprises:

a comparator having a first input coupled to the bus line and a second input coupled to receive a reference voltage;

measurement logic coupled to receive an output from the comparator, the measurement logic to measure at least one of a duty cycle, a frequency, or a period of the output from the comparator;

a discharge switch coupled to selectively discharge the bus line; and

discharge logic coupled to receive the output from the comparator and to control the discharge switch in response to the output from the comparator.

13. The apparatus of claim 11, further comprising a means for generating a voltage, and wherein the means for time-sharing further comprises:

a voltage line coupled to the means for generating the voltage; and

a plurality of voltage line switches, each coupled between the voltage line and one of the I/O means, wherein the means for controlling is further coupled to selectively couple the means for generating the voltage to any of the I/O means via control of the voltage line switches.

14. The apparatus of claim 11, wherein the means for controlling comprises:

a multi-bit register to store a multi-bit value, wherein the bus line switches are controlled responsive to the multi-bit value; and

a processor coupled to the multi-bit register to program the multi-bit register with the multi-bit value.

15. A method, comprising:

sequentially connecting each one of a plurality of variable capacitance switches of a capacitance sense user interface to a signal source via an input/output (“

I/O”

) multiplexer bus;

reciprocally charging and discharging each of the variable capacitance switches through the I/O multiplexer bus; and

sequentially connecting each one of the plurality of variable capacitance switches to capacitance measurement circuitry via the I/O multiplexer bus to monitor a capacitance of each of the variable capacitance switches.

16. The method of claim 15, further comprising time sharing the capacitance measurement circuitry across a plurality of I/O ports each coupled to one of the variable capacitance switches to monitor the capacitance of each of the variable capacitance switches by iteratively reprogramming the I/O multiplexer bus under control of a processor.

17. The method of claim 16, wherein iteratively reprogramming the I/O multiplexer bus comprises programming a multi-bit register to open and close switches within the I/O multiplexer bus coupled to each of the I/O ports according to a sequence.

18. The method of claim 16, wherein:

the I/O multiplexer bus comprises a bus line coupled to the capacitance measurement circuitry and a plurality of bus line switches each coupled between one of the I/O ports and the bus line,

the signal source comprises a current source, and

reciprocally charging and discharging each of the variable capacitance switches through the I/O multiplexer bus comprises programming a multi-bit register to close each of the bus line switches in turn while the other bus lines switches are open.

19. The method of claim 18, wherein the measurement circuitry comprises:

a comparator having a first input coupled to the bus line and a second input coupled to receive a reference voltage;

measurement logic coupled to receive an output from the comparator, the measurement logic to measure at least one of a duty cycle, a frequency, or a period of the output from the comparator;

a discharge switch coupled to selectively discharge the bus line; and

discharge logic coupled to receive the output from the comparator and to control the discharge switch in response to the output from the comparator.

20. The method of claim 16, wherein:

the I/O multiplexer bus comprises a bus line coupled to the capacitance measurement circuitry, a plurality of bus line switches each coupled between one of the I/O ports and the bus line, a voltage line coupled to the signal source, and a plurality of voltage line switches each coupled between the voltage line and one of the I/O ports;

the signal source comprises a voltage source, and

reciprocally charging and discharging each of the variable capacitance switches through the I/O multiplexer bus comprises charging each of the variable capacitance switches with the voltage source and discharging each of the variable capacitance switches into a summing capacitor coupled to another one of the I/O ports.