MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS

• US 20080313369A1
• Filed: 06/14/2007
• Published: 12/18/2008
• Est. Priority Date: 06/14/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Walls, Andrew Dale, Verdoorn, William Garrett
• Granted Patent: US 7,783,813 B2
• Time in Patent Office: Days
• US Class Current: 710/62
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Claims

1. A system, comprising:

a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics;

a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and

a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

2. The system of claim 1, wherein the communication interfaces and processor fabrics utilize different technologies, wherein the processor cards in each of the first and second nodes that communicate over their processor fabrics function as first and second symmetrical multi-processors.

3. The system of claim 2, wherein the processor cards in different nodes do not communicate with each other using the processor fabric technology.

4. The system of claim 1, further comprising:

a plurality of midplanes, wherein each midplane includes at least two processor cards, and wherein each of the first and second nodes includes at least one processor card from each midplane.

5. The system of claim 4, wherein each midplane is included within a storage server.

6. The system of claim 4, wherein each midplane includes an Input/Output (I/O) adaptor enabling communication with an external device, wherein each processor card in each midplane is connected to the I/O adaptor on the midplane using a communication interface different from the processor fabric interface.

7. The system of claim 1, further comprising:

cables, wherein the cables connect the processor fabrics of the processor cards in the first node and connect the processor fabrics of the processor cards in the second node.

8. The system of claim 1, further comprising:

node management code executed by at least one processor card in each of the first and second nodes to perform operations, the operations comprising;

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node not including the failed processor card in response to the determining that the node does not include at least one operational processor card.

9. The system of claim 1, further comprising:

node management code executed by at least one processor card in each of the first and second nodes to perform operations, the operations comprising;

detecting a failure of one processor card in one of the first or second node;

performing a failover to use the first or second node that does not include the failed processor card.

10. A system, comprising:

a first midplane including;

a first and second processor cards, wherein each processor card includes a processor fabric; and

a first communication interface connecting the first and second processor cards to enable communication between the first and second processor cards; and

a second midplane including;

a third and fourth processor cards, wherein each processor card includes a processor fabric, wherein the first and third processor cards connect via their processor fabrics and wherein the second and fourth processor cards connect via their processor fabrics; and

a second communication interface connecting the third and fourth processor cards to enable communication between the third and fourth processor cards.

11. The system of claim 10, wherein the communication interfaces and processor fabrics utilize different technologies, wherein the connected first and third processor cards and connected second and fourth processor cards function as first and second symmetrical multi-processors.

12. The system of claim 10, wherein each midplane is included within a storage server.

13. The system of claim 12, wherein each midplane includes an Input/Output (I/O) adaptor enabling communication with an external device, wherein each processor card in each midplane is connected to the I/O adaptor on the midplane using a communication interface different from the processor fabric.

14. The system of claim 10, further comprising:

cables, wherein the cables connect the processor fabrics of the first and third processor cards and the processor fabrics of the second and fourth processor cards.

15. The system of claim 10, further comprising:

management code executed by at least one processor card to perform operations, the operations comprising;

detecting a failure of one processor card;

determining whether the failed processor card is connected via the processor fabrics to an operational processor card;

reconfiguring the failed and operational cards connected via their processor fabrics to operate without the failed processor in response to the determining that the failed processor card is connected via the processor fabrics to the operational processor card; and

performing a failover to use the processor cards connected via their processor fabrics that are not connected via processor fabrics to the failed processor card in response to the determining that the failed processor card is not connected via the processor fabrics to the operational processor card.

16. The system of claim 10, further comprising:

management code executed by at least one processor card to perform operations, the operations comprising;

detecting a failure of one processor card;

performing a failover to use processor cards connected via their processor fabrics that are not connected via processor fabrics to the failed processor card.

17. A method, comprising:

configuring a first node comprising a plurality of processor cards, each having a processor fabric, connected via their processor fabrics;

configuring a second node comprising a plurality of processor cards, each having a processor fabric, connected via their processor fabrics;

configuring a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

18. The method of claim 17, wherein the communication interfaces and processor fabrics utilize different technologies, wherein configuring the first and second nodes and the processor fabrics comprises configuring the first and second nodes to function as a first and second symmetrical multi-processors, respectively.

19. The method of claim 17, wherein configuring the first and second nodes and processor fabrics further comprises:

configuring a plurality of midplanes, wherein each midplane includes at least two processor cards, and wherein each of the first and second nodes includes at least one processor card from each midplane.

20. The method of claim 17, further comprising:

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node not including the failed processor card in response to the determining that the node does not include at least one operational processor card.

21. The method of claim 17, further comprising:

detecting a failure of one processor card in one of the first or second node; and

performing a failover to use the first or second node that does not include the failed processor card.

22. An article of manufacture comprising code implemented in processor cards each having a processor fabric and coupled to one of a plurality of communication interfaces, wherein the code causes operations to be performed, the operations comprise:

configuring a first node comprising a plurality of the processor cards connected via their processor fabrics;

configuring a second node comprising a plurality of the processor cards connected via their processor fabrics;

configuring the communication interfaces, wherein each communication interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

23. The article of manufacture of claim 22, wherein the communication interfaces and processor fabrics utilize different technologies, wherein configuring the first and second nodes and the processor fabrics comprises configuring the first and second nodes to function as a first and second symmetrical multi-processors, respectively.

24. The article of manufacture of claim 22, wherein configuring the first and second nodes and processor fabrics further comprises:

configuring a plurality of midplanes, wherein each midplane includes at least two processor cards, and wherein each of the first and second nodes includes at least one processor card from each midplane.

25. The article of manufacture of claim 22, wherein the operations further comprise:

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor to operate without the failed processor in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node not including the failed processor card in response to the determining that the node does not include at least one operational processor card.

26. The article of manufacture of claim 22, wherein the operations further comprise:

detecting a failure of one processor card in one of the first or second node; and

performing a failover to use the first or second node that does not include the failed processor card.