PIPELINE DEVICE WITH A PLURALITY OF PIPELINED PROCESSING UNITS

• US 20080313439A1
• Filed: 06/13/2008
• Published: 12/18/2008
• Est. Priority Date: 06/15/2007
• Status: Abandoned Application

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: SUZUKI, Yousuke
• Application Number:
  US12/138,723
• Publication Number:
  US 20080313439A1
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

In a pipeline device, the output of each of processing units is connected to a corresponding one of data output lines of data transfer lines. Input selectors are provided for the processing units, respectively. Each input selector selects one of the data transfer lines except for one data output line to which the output of a corresponding one processing unit is connected to thereby determine one of interconnection patterns among the processing units. The interconnection patterns correspond to data-processing tasks, respectively. Each input selector inputs, to a corresponding one of the processing units, data flowing through the selected one of the data transfer lines. Each processing unit individually performs a predetermined process based on data inputted thereto by a corresponding one of the input selectors to thereby perform, in pipeline, one of the data-processing tasks corresponding to the determined one of the interconnection patterns.

Claims

1. A pipeline device comprising:

a plurality of data transfer lines including;

a data input line through which data is inputted, and a plurality of data output lines;

a plurality of processing units each having an input and an output, the output of each of the plurality of processing units being connected to a corresponding one of the data output lines, and

a plurality of input selectors provided for the plurality of processing units, respectively, each of the plurality of input selectors working to;

select one of the plurality of data transfer lines except for one data output line to which the output of a corresponding one of the plurality of processing units is connected to thereby determine one of a plurality of interconnection patterns among the plurality of processing units, the plurality of interconnection patterns corresponding to a plurality of data-processing tasks, respectively; and

input, to a corresponding one of the plurality of processing units via the input thereof, data flowing through the selected one of the plurality of data transfer lines, each of the plurality of processing units working to individually carry out a predetermined process based on data inputted thereto by a corresponding one of the plurality of input selectors to thereby carry out, in pipeline, one of the plurality of data-processing tasks corresponding to the determined one of the plurality of interconnection patterns.

2. A pipeline device according to claim 1, wherein the pipeline device is connected to a controller, the controller working to input, to the pipeline device, a control signal, the control signal representing one of the plurality of interconnection patterns, each of the plurality of input selectors working to select one of the plurality of data transfer lines except for one data output line to which the output of a corresponding one of the plurality of processing units is connected in accordance with the control signal to thereby determine one of the plurality of interconnection patterns among the plurality of processing units.

3. A pipeline device according to claim 1, wherein the plurality of processing units are a plurality of convolution units, each of the plurality of convolution units having a kernel coefficient matrix with a predetermined size and working to convolve data inputted thereto based on the kernel coefficient matrix and output a convolved result, further comprising:

a combining unit connected to each of the plurality of convolution units and working to combine the convolved results outputted from the plurality of convolution units to thereby carry out a convolution based on a kernel coefficient matrix with a size greater than the size of the kernel coefficient matrix of each of the plurality of convolution units.

4. A pipeline device according to claim 3, wherein the plurality of convolution its work to respectively output the convolved results at different timings, the combining unit comprises a delay circuit and a total sum calculating unit,

the delay circuit being configured to:

temporarily store at least one of the convolved results outputted from the plurality of convolution units so as to delay the at least one of the convolved results by a predetermined period; and

output, to the total sum calculating circuit, the at least one of the convolved results delayed thereby such that the convolved results outputted from the plurality of convolution units are inputted to the total sum calculating circuit in synchronization with each other,

the total sum calculating circuit working to;

receive the convolved results inputted thereto; and

calculate a sum of the received convolved results to thereby obtain a result of the convolution based on the kernel coefficient matrix with the size greater than the size of the kernel coefficient matrix of each of the plurality of convolution units.

5. A pipeline device according to claim 1, further comprising:

a plurality of enable-signal transfer lines including;

an enable-signal input line through which an enable signal is inputted, and a plurality of enable signal output lines;

a plurality of delay units provided for the plurality of processing units, respectively, each of the plurality of delay units having an input and an output, the output of each of the plurality of delay units being connected to a corresponding one of the enable-signal output lines, each of the plurality of delay units working to;

receive the enable signal, the enable signal enabling a corresponding one of the plurality of processing unit to input data; and

delay an output of the received enable signal by a predetermined period required for a corresponding one of the plurality of processing units to perform the corresponding predetermined process and to output a result of the corresponding predetermined process;

a plurality of first signal input selectors provided for the plurality of delay units, each of the plurality of first signal input selectors working to;

select one of the plurality of enable-signal transfer lines except for one enable-signal output line to which the output of a corresponding one of the plurality of delay units is connected; and

input, to a corresponding one of the plurality of delay units, an enabling signal flowing through the selected one of the plurality of enable-signal transfer lines to thereby determine one of a plurality of interconnection patterns among the plurality of first signal input selectors to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units; and

a plurality of second signal input selectors provided for the plurality of processing units and connected to the plurality of enable-signal transfer lines, respectively, each of the plurality of second signal input selectors working to;

select one of the plurality of enable-signal transfer lines; and

input, to a corresponding one of the plurality of processing units, an enabling signal flowing through the selected one of the plurality of enable-signal transfer lines to thereby determine one of a plurality of enable-signal input patterns between the plurality of second signal input selectors and the plurality of processing units to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units.

6. A pipeline device according to claim 1, further comprising:

a plurality of enable-signal transfer lines including an enable-signal input line through which an enable signal is inputted, and a plurality of enable signal output lines, each of the plurality of enable signal output lines being connected to an alternative output of a corresponding one of the plurality of processing unit;

a plurality of signal input selectors provided for the plurality of processing units, respectively, each of the plurality of signal input selectors working to;

select one of the plurality of enable-signal transfer lines; and

input, to a corresponding one of the plurality of processing units, an enabling signal flowing rough the selected one of the plurality of enable-signal transfer lines to thereby determine one of a plurality of interconnection patterns among the plurality of signal input selectors to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units,

each of the plurality of processing units working to;

receive the enable signal, the enable signal enabling a corresponding one of the plurality of processing unit to input data; and

delay an output of the received enable signal by a predetermined period required for a corresponding one of the plurality of processing units to perform the corresponding predetermined process and to output, to a corresponding one of the plurality of enable-signal output lines, a result of the corresponding predetermined process.

7. A pipeline device according to claim 5, wherein the pipeline device is connected to a microcomputer, the microcomputer working to carry out information processing based on a result of the predetermined process by each of the plurality of processing units, further comprising:

an interrupt input unit working to input, to the microcomputer, an interrupt request in accordance with the enable signal flowing through each of the enable signal output lines, the interrupt request allowing the microcomputer to grasp timing of data to be inputted to each of the plurality of processing units.

8. A pipeline device according to claim 6, wherein the pipeline device is connected to a microcomputer, the microcomputer working to carry out information processing based on a result of the predetermined process by each of the plurality of processing units, further comprising:

an interrupt input unit working to input, to the microcomputer, an interrupt request in accordance with the enable signal flowing through each of the enable signal output lines, the interrupt request allowing the microcomputer to grasp timing of data to be inputted to each of the plurality of processing units.

9. A pipeline device according to claim 1, wherein the data is pixel data of each pixel of frame video data corresponding to a frame video image, the pixel data is inputted to the data-processing apparatus through the data input line pixel by pixel, and the plurality of data-processing tasks include a preprocessing task of a gradient method for optical-flow estimation, an edge-detection task, a preprocessing task of labeling, and a filtering task with a 5×

5 kernel coefficient matrix.

10. A data-processing apparatus comprising:

a plurality of data transfer lines including;

a data input line through which data is inputted, and a plurality of data output lines;

a plurality of processing units each having an input and an output, the output of each of the plurality of processing units being connected to a corresponding one of the data output lines;

a plurality of input selectors provided for the plurality of processing units, respectively; and

a controller working to input, to the plurality of input selectors, a control signal representing one of a plurality of interconnection patterns among the plurality of processing units, the plurality of interconnection patterns corresponding to a plurality of data-processing tasks, respectively,

each of the plurality of input selectors working to;

select one of the plurality of data transfer lines except for one data output line to which the output of a corresponding one of the plurality of processing units is connected to thereby determine one of the plurality of interconnection patterns among the plurality of processing units; and

input, to a corresponding one of the plurality of processing units via the input thereof, data flowing through the selected one of the plurality of data transfer lines, each of the plurality of processing units working to individually can out a predetermined process based on data inputted thereto by a corresponding one of the plurality of input selectors to thereby carry out, in pipeline, one of the plurality of data-processing tasks corresponding to the determined one of the plurality of interconnection patterns.

11. A data-processing apparatus according to claim 10, wherein the data is pixel data of each pixel of frame video data corresponding to a frame video image, the pixel data is inputted to the data-processing apparatus through the data input line pixel by pixel, and the plurality of data-processing tasks include a preprocessing task of a gradient method for optical-flow estimation, an edge-detection task, a preprocessing task of labeling, and a filtering task with a 5×

5 kernel coefficient matrix.

12. A data-processing apparatus according to claim 10, further comprising:

a plurality of enable-signal transfer lines including;

an enable-signal input line through which an enable signal is inputted, and a plurality of enable signal output lines;

a plurality of delay units provided for the plurality of processing units, respectively, each of the plurality of delay units having an input and an output, the output of each of the plurality of delay units being connected to a corresponding one of the enable-signal output lines, each of the plurality of delay units working to;

receive the enable signal, the enable signal enabling a corresponding one of the plurality of processing unit to input data; and

delay an output of the received enable signal by a predetermined period required for a corresponding one of the plurality of processing units to perform the corresponding predetermined process and to output a result of the corresponding predetermined process;

a plurality of first signal input selectors operatively connected to the controller and provided for the plurality of delay units, each of the plurality of first signal input selectors working to;

select one of the plurality of enable-signal transfer lines except for one enable-signal output line to which the output of a corresponding one of the plurality of delay units is connected; and

input, to a corresponding one of the plurality of delay units, an enabling signal flowing through the selected one of the plurality of enable-signal transfer lines under control of the controller to thereby determine one of a plurality of interconnection patterns among the plurality of first signal input selectors to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units; and

a plurality of second signal input selectors operatively connected to the controller and provided for the plurality of processing units and connected to the plurality of enable-signal transfer lines, respectively, each of the plurality of second signal input selectors working to;

select one of the plurality of enable-signal transfer lines; and

input, to a corresponding one of the plurality of processing units, an enabling signal flowing through the selected one of the plurality of enable-signal transfer lines under control of the controller to thereby determine one of a plurality of enable-signal input patterns between the plurality of second signal input selectors and the plurality of processing units to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units.

13. A data-processing apparatus according to claim 10, further comprising:

a plurality of enable-signal transfer lines including;

an enable-signal input line trough which an enable signal is inputted, and a plurality of enable signal output lines, each of the plurality of enable signal output lines being connected to an alternative output of a corresponding one of the plurality of processing units;

a plurality of signal input selectors operatively connected to the controller and provided for the plurality of processing units, respectively, each of the plurality of signal input selectors working to;

select one of the plurality of enable-signal transfer lines; and

input, to a corresponding one of the plurality of processing units, an enabling signal flowing through the selected one of the plurality of enable-signal transfer lines under control of the controller to thereby determine one of a plurality of interconnection patterns among the plurality of signal input selectors to be matched with the determined one of the plurality of interconnection patterns among the plurality of processing units,

each of the plurality of processing units working to;

receive the enable signal, the enable signal enabling a corresponding one of the plurality of processing unit to input data; and

delay an output of the received enable signal by a predetermined period required for a corresponding one of the plurality of processing units to perform the corresponding predetermined process and to output, to a corresponding one of the plurality of enable-signal output lines, a result of the corresponding predetermined process.