Integrated circuit protection and detection grid

• US 20080313746A1
• Filed: 06/12/2007
• Published: 12/18/2008
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: ITT Manufacturing Enterprises, Inc. (ITT, Inc.)
• Inventors: Doi, Bryan Cary
• Granted Patent: US 7,723,998 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 27/02 including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A mesh of conductors forms a grid in a multi-layered electronic device. The mesh of conductors includes (1) a first set of conductors disposed in one layer forming parallel lines in the one layer, and (2) a second set of conductors disposed in another layer forming parallel lines in the other layer. The first set of conductors is configured to provide a first voltage reference, and the second set of conductors is configured to provide a second voltage reference. At least one grid check circuit is coupled to the first set of conductors and the second set of conductors for monitoring presence and/or absence of the first or second voltage references. The parallel lines formed in the one layer and the parallel lines formed in the other layer are substantially perpendicular to each other.

Claims

1. A protection circuit for integrity monitoring of an electronic device comprising

a first grid check line interleaved between a first set of conductor lines, each distributing a first potential reference to the electronic device,

a second grid check line interleaved between a second set of conductor lines, each distributing a second potential reference to the electronic device, and

a grid check circuit coupled to the first and second grid check lines,

wherein the first and second grid check lines are configured to provide first and second voltage references, respectively, to the grid check circuit for monitoring the integrity of the electronic device.

2. The protection circuit of claim 1, wherein

the first and second potential references are VDD and VSS, respectively,

the first and second voltage references are SSS and SDD, respectively, and

the VDD potential reference is substantially similar to the SDD voltage reference, and the VSS potential reference is substantially similar to the SSS voltage reference.

3. The protection circuit of claim 1, wherein

the electronic device is a multi-layered device,

the first grid check line and the first set of conductor lines are disposed in one single layer of the multi-layered device, and

the second grid check line and the second set of conductor lines are disposed in another single layer of the multi-layered device.

4. The protection circuit of claim 1, wherein

the electronic device includes metallization layers,

the first and second sets of conductor lines, respectively, are embedded in adjacent metallization layers for forming a power distribution grid in the electronic device, and

the first and second grid check lines, respectively, are embedded in the same adjacent metallization layers for forming a voltage difference in the grid check circuit.

5. The protection circuit of claim 1, wherein

the electronic device includes metallization layers,

the first set of conductor lines are connected to each other and are longitudinally distributed in one metallization layer,

the second set of conductors lines are connected to each other and are transversely distributed in another metallization layer,

the first grid check line includes a plurality of first grid check lines connected to each other and longitudinally distributed in the one metallization layer, and the second grid check line includes a plurality of second grid check lines connected to each other and transversely distributed in the other metallization layer.

6. The protection circuit of claim 1, wherein

the first grid check line includes a plurality of first grid check lines connected to each other,

the second grid check line includes a plurality of second grid check lines connected to each other, and

the first and second grid check lines are orthogonally oriented to each other to form a mesh of lines.

7. The protection circuit of claim 1, wherein

the grid check circuit includes a least two separate grid check circuits disposed in different portions of the electronic device.

8. The protection circuit of claim 1, further including

a fault collector circuit, coupled to the grid check circuit, for providing to a user a status of the integrity of the electronic device.

9. The protection circuit of claim 1, further including

a state machine for placing the first and second voltage references on the first and second grid check lines, respectively, and

wherein the grid check circuit verifies that the first and second voltage references are present on the first and second grid check lines, respectively.

10. The protection circuit of claim 1, further including

a state machine for separately activating and turning-off the first and second voltage references on the first and second grid check lines, respectively, and wherein

the grid check circuit sequentially verifies that the first voltage reference is present on and then absent from the first grid check line, and

the grid check circuit sequentially verifies that the second voltage reference is present on and then absent from the second grid check line.

11. The protection circuit of claim 1, wherein

the electronic device includes an integrated circuit (IC) having multiple layers of metallization.

12. The protection circuit of claim 1, wherein

the electronic device is a high density package and includes a silicon substrate.

13. A mesh of conductors forming a grid in a multi-layered electronic device comprising

a first set of conductors disposed in one layer forming parallel lines in the one layer,

a second set of conductors disposed in another layer forming parallel lines in the other layer,

the first set of conductors configured to provide a first voltage reference, and the second set of conductors configured to provide a second voltage reference,

at least one grid check circuit, coupled to the first set of conductors and the second set of conductors, for monitoring presence and/or absence of at least one of the first or second voltage references.

14. The mesh of conductors of claim 13, wherein

the parallel lines in the one layer and the parallel lines in the other layer are substantially perpendicular to each other.

15. The mesh of conductors of claim 13, wherein

the multi-layered electronic device includes a first set of power lines and a second set of power lines for providing a potential difference to the electronic device, and

the first and second set of power lines are different from the first and second set of conductors.

16. The mesh of conductors of claim 15, wherein

the first set of power lines provides a positive voltage reference to the electronic device,

the first set of conductors provides a ground voltage reference, and

the first set of power lines is interleaved with the first set of conductors in the one layer.

17. The mesh of conductors of claim 16, wherein

the second set of power lines provides a ground voltage reference to the electronic device,

the second set of conductors provides a positive voltage reference, and

the second set of power lines is interleaved with the second set of conductors in the other layer.

18. The mesh of conductors of claim 13, further including

a controller, coupled to the at least one grid check circuit, for enabling and disabling the first and second voltage references,

wherein the at least one grid check circuit is configured to detect the enabling and/or the disabling of the first or second voltage references.

19. The mesh of conductors of claim 18, wherein

the controller is configured to periodically enable and disable the first and second voltage references, and

the at least one grid check circuit is configured to correspondingly periodically detect the enabling and/or disabling of the first or second voltage references.

20. A method for integrity monitoring of a multi-layered electronic device, comprising the steps of:

(a) distributing a first potential reference by way of one conducting layer of the electronic device;

(b) distributing a second potential reference by way of another conducting layer of the electronic device;

(c) distributing a first voltage reference, which is different from the first potential reference in the one conducting layer;

(d) distributing a second voltage reference, which is different from the second potential reference in the other conducting layer; and

(e) periodically monitoring the distribution of the first and second voltage references to determine the integrity of the multi-layered electronic device.