METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC CIRCUIT BOARD

• US 20080313893A1
• Filed: 06/10/2008
• Published: 12/25/2008
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated)
• Inventors: Nakasu, Nobuaki
• Granted Patent: US 8,112,883 B2
• Time in Patent Office: Days
• US Class Current: 29/830
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H05K 3/225 Correcting or repairing of printed circuits H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/515 to trim electric component
• CPC Class Codes: Y10T 29/53004 with means to regulate operation by use of templet, tape, card or other replaceable information supply

Abstract

A method for manufacturing an electronic circuit board which contains an electronic circuit on a main surface of a glass substrate according to the invention sequentially performs a step of electrically inspecting the main surface of the glass substrate on which the electronic circuit is formed, a step of specifying positions and defect types of defects on the main surface of the glass substrate, a step of calculating reference point coordinates on the main surface of the glass substrate and correcting the coordinates, a step of extracting respective defects from an image around the defects and specifying a defect to be corrected in the extracted defects by referring to a defect existing range registered in advance for each defect type, and a step of cutting the specified defect. By this method, a foreign material adhering to the glass substrate is not erroneously judged as short-circuit defect causing short-circuit on the electronic circuit, and only defect actually requiring correction can be removed.

Claims

1. A method for manufacturing an electronic circuit board on which repeated electrode patterns such as wirings are formed, comprising the steps of:

detecting a defect caused by short-circuit between electrodes of a circuit on the electronic circuit board;

specifying correction target defect based on defect existing area information stored in advance in association with defect type after specifying the position and the defect type of the detected defect; and

cutting and correcting a short-circuit defect portion based on the cutting position information stored in advance in association with the defect type and the defect existing area information.

2. The method for manufacturing the electronic circuit board according to claim 1, further comprising the step of making judgment of completion of the correction and generating warning when it is judged that the correction is not finished.

3. The method for manufacturing the electronic circuit board according to claim 1, wherein numbers given for each minimum repetition unit of the repeated electrode patterns are used as information for specifying the defect position.

4. The method for manufacturing the electronic circuit board according to claim 1, wherein numbers given to two wirings selected in inspection for each minimum repetition unit of the repeated electrode patterns are used as information for specifying the defect position.

5. The method for manufacturing the electronic circuit board according to claim 1, wherein the defect existing area information is stored by using relative coordinates from a reference point position determined as one position for each minimum unit of the repeated patterns.

6. The method for manufacturing the electronic circuit board according to claim 1, wherein the defect existing area information is stored by using relative coordinates from a cross point of two wirings selected in inspection for each minimum repetition unit of the repeated patterns.

7. The method for manufacturing the electronic circuit board according to claim 1, wherein:

a plurality of defect existing areas are stored as the defect existing area information;

one defect existing area or a combination of at least two defect existing areas are stored; and

priority is defined for each combination.

8. The method for manufacturing the electronic circuit board according to claim 1, wherein the step of specifying the correction target defect judges that correction target defect exists when defect is detected in the area stored as the defect existing area information.

9. The method for manufacturing the electronic circuit board according to claim 1, wherein the step of specifying the correction target defect judges that correction target defect exists when a defect is detected in all the areas included in the one area or the combination of at least two areas stored as the defect existing area information.

10. The method for manufacturing the electronic circuit board according to claim 1, wherein the cutting position information is stored such that a plurality of cutting positions are associated with one defect existing area information.

11. The method for manufacturing the electronic circuit board according to claim 1, wherein the defect existing area information and the cutting position information are stored by using relative coordinates from a reference point set in the vicinity of the defect.

12. An apparatus for manufacturing an electronic circuit board on which repeated patterns are formed, comprising:

a correction device which corrects the electronic circuit board;

a short-circuit defect detecting part;

a defect position specifying part;

a defect type specifying part;

a reference point coordinates part;

a reference point coordinates correcting part;

a defect image acquiring part;

a defect extracting part;

a correction target defect specifying part;

a cutting position specifying part;

a cutting part; and

a storing part which stores inspection condition information, inspection result information, circuit design information, defect existing area information, and cutting position information.

13. The apparatus for manufacturing the electronic circuit board according to claim 12, further comprising:

a communication part which receives defect position and defect type from an inspection device;

a reference point coordinates calculating part;

a reference point coordinates correcting part;

a defect image acquiring part;

a defect extracting part;

a correction target defect specifying part;

a cutting position specifying part;

a cutting part; and

a storing part which stores inspection condition information, inspection result information, circuit design information, defect existing area information, and cutting position information.

14. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the defect position specifying part has a function of outputting numbers given to each minimum repetition unit of the repeated patterns.

15. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the defect position specifying part has a function of outputting numbers given to two wirings selected in inspection for each minimum repetition unit of the repeated patterns.

16. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the correction target defect specifying part has a function of storing relative coordinates from a reference point position determined as one position for each minimum unit of the repeated patterns.

17. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the correction target defect specifying part has a function of storing relative coordinates from a cross point of two wirings selected in inspection for each minimum repetition unit of the repeated patterns.

18. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the correction target defect specifying part has a unit for storing a plurality of defect existing areas, a unit for storing one area or a combination of at least two areas, and a unit for storing priority defined for each combination.

19. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the correction target defect specifying part has a function of judging that correction target defect exists when defect is detected in the defect existing area.

20. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the correction target defect specifying part has a function of judging that correction target defect exists when a defect is detected in all the areas included in the one area or the combination of at least two defect existing areas stored as the defect existing area.

21. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the cutting position specifying part has a function of storing a plurality of cutting positions in association with one defect existing area.

22. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the cutting part has a function of displaying a cutting position overlapped on a monitor showing a correction portion.

23. The apparatus for manufacturing the electronic circuit board according to claim 12, wherein the cutting part has a unit for obtaining an image of a cutting portion after execution of cutting and judging completion of cutting, and a unit for generating warning when judgment of cutting completion is not made even after execution of cutting and cutting completion judgment predetermined times.