IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME

• US 20080315198A1
• Filed: 12/31/2007
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Jung, Oh Jin
• Application Number:
  US11/967,380
• Publication Number:
  US 20080315198A1
• Time in Patent Office: Days
• US Class Current: 257/53
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer

Abstract

An image sensor and a manufacturing method thereof are provided. The sensor includes a substrate, a bottom electrode, an intrinsic layer and a first conductive layer formed over the substrate, a diffusion barrier film formed over the first conductive layer, and an upper transparent electrode formed over the diffusion barrier film. Therefore, a vertical integration of a transistor circuitry and a photodiode can be provided. Further, the leakage current is prevented and the photosensitivity is increased by performing the plasma treatment on the first conductive layer. Due to the vertically integrated transistor circuitry and photodiode, the fill factor can approach 100%, and higher sensitivity compared with the related art having the same pixel size can be provided. The sensitivity of each unit pixel is not reduced, even though more complex circuitry is realized on the image sensor.

Claims

1. An apparatus comprising:

a substrate having at least one circuit element;

a bottom electrode, an intrinsic layer, a first conductive layer sequentially formed over the substrate;

a diffusion barrier film formed over the first conductive layer; and

an upper transparent electrode formed over the diffusion barrier film.

2. The apparatus of claim 1, wherein the diffusion barrier film has an oxygen concentration of approximately 60% or less.

3. The apparatus of claim 1, wherein the diffusion barrier film is a layer having nitrogen diffused on the first conductive layer.

4. The apparatus of claim 1, comprising a second conductive layer formed between the bottom electrode and the intrinsic layer.

5. The apparatus of claim 1, wherein the substrate includes metal wiring and electron transfer wiring.

6. The apparatus of claim 1, wherein said substrate comprises transistor circuitry vertically integrated with said bottom electrode, intrinsic layer, first conductive layer, diffusion barrier, and upper electrode.

7. The apparatus of claim 1, wherein said bottom electrode, intrinsic layer, and first conductive layer form a PIN diode.

8. The apparatus of claim 1, wherein said first conductive layer is amorphous silicon.

9. A method comprising:

forming a bottom electrode, an intrinsic layer, and a first conductive layer sequentially over a substrate including at least one circuit element;

forming a diffusion barrier film over the first conductive layer; and

forming an upper transparent electrode over the diffusion barrier film.

10. The method of claim 9, wherein the diffusion barrier film is formed over the first conductive layer by performing a plasma treatment on the surface of the first conductive layer.

11. The method of claim 10, wherein the plasma treatment is carried out using N₂ gas at a temperature of approximately 100°

C. to 400°

C.

12. The method of claim 11, wherein the plasma treatment is carried out using N₂ gas at a pressure of 10 mtorr to 100 mtorr.

13. The method of claim 9, wherein the diffusion barrier film is formed over the first conductive layer by performing a gas cluster ion beam treatment.

14. The method of claim 9, wherein the gas cluster ion beam treatment is carried out by using a gas cluster ion beam with a scale of approximately 100 to 9,000 microns formed using N₂ gas, to form the diffusion barrier film over the first conductive layer.

15. The method of claim 9, wherein the diffusion barrier film has an oxygen concentration of approximately 60% or less.

16. The method of claim 9, comprising forming a second conductive layer over the bottom electrode, and forming the intrinsic layer over the second conductive layer.

17. The method of claim 9, comprising forming electron transfer wiring inside the substrate.

18. The method of claim 17, comprising forming a barrier metal between the electron transfer wiring and the bottom electrode.

19. The method of claim 9, comprising vertically integrating transistor circuitry with said bottom electrode, intrinsic layer, first conductive layer, diffusion barrier, and upper electrode.

20. The method of claim 9, comprising forming a PIN diode from said bottom electrode, intrinsic layer, and first conductive layer.