Atomic Layer Deposition Method and Semiconductor Device Formed by the Same

• US 20080315292A1
• Filed: 06/17/2008
• Published: 12/25/2008
• Est. Priority Date: 06/22/2007
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Mieno, Fumitake, Ji, Hua, Chi, Min-Hwa, Zhang, Seanfuxiong
• Granted Patent: US 8,158,512 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

Claims

1. An atomic layer deposition method, comprising the steps of:

placing a semiconductor substrate in an atomic layer deposition chamber;

flowing a first precursor gas to the semiconductor substrate within the atomic layer deposition chamber to form a first discrete monolayer on the semiconductor substrate;

flowing an inert purge gas to the semiconductor substrate within the atomic layer deposition chamber to remove the first precursor gas which does not form the first monolayer on the semiconductor substrate;

flowing a second precursor gas to the atomic layer deposition chamber to react with the first precursor gas which forms the first monolayer, thereby forming a first discrete compound monolayer;

flowing an inert purge gas to the semiconductor substrate within the atomic layer deposition chamber to remove the second precursor gas which does not react with the first precursor gas and a byproduct of the reaction between the first and the second precursor gases;

forming a first dielectric layer to cover the first discrete compound monolayer on the semiconductor substrate;

flowing a third precursor gas to the atomic layer deposition chamber to form a third discrete monolayer above first dielectric layer;

flowing an inert purge gas to the atomic layer deposition chamber to remove the third precursor gas which does not form the third monolayer with the first dielectric layer;

flowing a forth precursor gas to the atomic layer deposition chamber to react with the third precursor gas which has formed the third monolayer, thereby forming a second discrete compound monolayer;

flowing an inert purge gas to the atomic layer deposition chamber to remove the forth precursor gas which does not react with the third monolayer and a byproduct of the reaction between the third and the forth precursor gases; and

forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer.

2. The atomic layer deposition method in claim 1, further comprising forming a third discrete compound monolayer on the second dielectric layer;

forming a third dielectric layer to cover the third discrete compound monolayer above the second dielectric layer;

. . . ; and

in the same way, forming a (N+1)^th discrete compound monolayer on the N^th dielectric layer, and forming a (N+1)^th dielectric layer to cover the (N+1)^th discrete compound monolayer above the N^th dielectric layer, where the N is an integer no less than 3.

3. The atomic layer deposition method in claim 1, wherein the first precursor is selected from one or more of metal, semiconductor, metal coordinated with halogen and organic complex, and semiconductor coordinated with halogen and organic complex, or mixtures thereof.

4. The atomic layer deposition method in claim 3, wherein the metal comprises Ta, Ti, W, Mo, Nb, Cu, Ni, Pt, Ru, Me, Ni or Al.

5. The atomic layer deposition method in claim 3 wherein the semiconductor is silicon.

6. The atomic layer deposition method in claim 3, wherein the metal coordinated with halogen and organic complex comprises Al(CH₃)₃, Hf[N(CH₃)(C₂H₅)]₄, Hf[N(C₂H₅)₂]₄, Hf[OC(CH₃)₃]₄, or HfCl₄, and the semiconductor coordinated with halogen and organic complex comprises SiCl₂H₂, Si(OC₂H₅)₄, Si₂Cl₆, SiH₂[NH(C₄H₉)]₂, or SiH(OC₂H₅)₃.

7. The atomic layer deposition method in claim 1, wherein when the first precursor is SiCl₂H₂, the first precursor flows to the semiconductor substrate in the atomic layer deposition chamber at a flow rate of 0.06˜

0.3 slm for 0˜

10 sec.

8. The atomic layer deposition method in claim 1, wherein the second precursor comprises NH₃, N₂O, N₂, O₂, O₃, or H₂O.

9. The atomic layer deposition method in claim 1, wherein the third precursor is selected from one or more of metal, semiconductor, metal coordinated with halogen and organic complex, and semiconductor coordinated with halogen and organic complex, or mixtures thereof.

10. The atomic layer deposition method in claim 9, wherein the metal comprises Ta, Ti, W, Mo, Nb, Cu, Ni, Pt, Ru, Me, Ni or Al.

11. The atomic layer deposition method in claim 9, wherein the semiconductor is silicon.

12. The atomic layer deposition method in claim 9, wherein the metal coordinated with halogen and organic complex comprises Al(CH₃)₃, Hf[N(CH₃)(C₂H₅)]₄, Hf[N(C₂H₅)₂]₄, Hf[OC(CH₃)₃]₄, or HfCl₄, and the semiconductor coordinated with halogen and organic complex comprises SiCl₂H₂, Si(OC₂H₅)₄, Si₂Cl₆, SiH₂[NH(C₄H₉)]₂, or SiH(OC₂H₅)₃.

13. The atomic layer deposition method in claim 9, wherein when the third precursor is SiCl₂H₂, the third precursor flows to the semiconductor substrate in the atomic layer deposition chamber at a flow rate of 0.06˜

0.3 slm for 0˜

10 sec.

14. The atomic layer deposition method in claim 1, wherein the fourth precursor gas comprises NH₃, N₂O, N₂, O₂, O₃, or H₂O.

15. The atomic layer deposition method in claim 1, wherein the process for forming the first dielectric layer is an atomic layer deposition process.

16. The atomic layer deposition method in claim 15, wherein the process for forming the first dielectric layer comprises the following steps:

(I) flowing a fifth precursor gas to the atomic layer deposition chamber to form a fifth monolayer above the semiconductor substrate and the first discrete compound monolayer, wherein the fifth monolayer fills the spacing in the first discrete compound monolayer;

(II) flowing an inert purge gas to the atomic layer deposition chamber to remove the fifth precursor gas that does not form the fifth monolayer above the semiconductor substrate and the first discrete compound monolayer;

(III) flowing a sixth precursor gas to the atomic layer deposition chamber to react with the fifth precursor gas that has formed the fifth monolayer, thereby forming a first dielectric mono-atomic layer;

(IV) flowing an inert purge gas to the atomic layer deposition chamber to remove the sixth precursor gas that does not form the first dielectric mono-atomic layer and the byproduct of the reaction between the fifth and the sixth precursor gases; and

repeating the steps (I) to (IV) until the resulting first dielectric layer has a given thickness to cover the first discrete compound monolayer.

17. The atomic layer deposition method in claim 1, wherein the first dielectric layer is made of silicon oxide.

18. A semiconductor device, comprising a semiconductor substrate, a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed above the semiconductor substrate, a gate disposed above the three-layer stack structure, and a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure, the charge trapping layer is a dielectric layer containing one or more discrete compound monolayers formed by ALD method.

19. The semiconductor device in claim 18, wherein the size of the discrete compound monolayer is at atomic level.

20. The semiconductor device in claim 18, wherein the discrete compound monolayer is made of silicon nitride, aluminum oxide, hafnium oxide or tungsten nitride.

21. The semiconductor device in claim 18 wherein the dielectric layer is made of silicon oxide.