Semiconductor die with backside passive device integration

• US 20080315356A1
• Filed: 06/06/2008
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Reisner, Russ
• Granted Patent: US 8,299,572 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads.

Claims

1. A semiconductor die comprising:

a backside surface opposite an active surface;

said active surface including at least one active device;

at least one passive device situated on said backside surface.

2. The semiconductor die of claim 1 further comprising an interconnect region situated over said active surface of said semiconductor die.

3. The semiconductor die of claim 2 further comprising at least one through-wafer via, wherein said at least one through-wafer via electrically connects said at least one passive device to said interconnect region.

4. The semiconductor die of claim 2, wherein said at least one passive device comprises an inductor having a first terminal and a second terminal, wherein said first terminal of said inductor is electrically connected to said interconnect region.

5. The semiconductor die of claim 4 further comprising at least one through-wafer via, wherein said at least one through-wafer via electrically connects said first terminal of said inductor to said active surface.

6. The semiconductor die of claim 4 further comprising at least one solder pad, wherein said at least one solder pad is situated on said backside surface and is electrically connected to said second terminal of said inductor.

7. The semiconductor die of claim 2, wherein said interconnect region includes a plurality of bond pads.

8. The semiconductor die of claim 2, wherein said interconnect region includes a plurality of solder bump pads.

9. The semiconductor die of claim 4, wherein said inductor has a thickness of between 1.0 micron and 20.0 microns.

10. The semiconductor die of claim 1, wherein said semiconductor die is utilized in a circuit board as a part of an electronic system, wherein said electronic system is selected from the group consisting of a wired or wireless communications device, a cell phone, a switching device, a router, a repeater, a codec, a wired or wireless LAN, a WLAN, a Bluetooth enabled device, a digital camera, a digital audio player and/or recorder, a digital video player and/or recorder, a computer, a monitor, a television set, a satellite set top box, a cable modem, a digital automotive control system, a digitally-controlled home appliance, a printer, a copier, a digital audio or video receiver, an RF transceiver, a personal digital assistant (PDA), a digital game playing device, a digital testing and/or measuring equipment, a digital avionics device, a medical device, and a digitally-controlled medical equipment.

11. A semiconductor die comprising:

a backside surface opposite an active surface;

said active surface including at least one active device;

an interconnect region situated over said active surface;

at least one input/output (I/O) pad situated on said backside surface, said at least one I/O pad being electrically connected to said interconnect region of said semiconductor die.

12. The semiconductor die of claim 11 further comprising at least one through-wafer via, wherein said at least one through-wafer via electrically connects said at least one I/O pad to said interconnect region of said semiconductor die.

13. The semiconductor die of claim 11 further comprising a metal layer situated over said backside surface, wherein said metal layer surrounds said at least one I/O pad.

14. The semiconductor die of claim 11, wherein interconnect region includes a plurality of wirebond pads.

15. A semiconductor die comprising:

a backside surface opposite an active surface;

said active surface including at least one active device;

an interconnect region situated over said active surface;

a passive circuit situated on said backside surface;

at least one through-wafer via electrically connecting said passive circuit to said interconnect region.

16. The semiconductor die of claim 15, wherein said passive circuit comprises a balun of a bulk acoustic wave (BAW) filter.

17. The semiconductor die of claim 15, wherein said interconnect region includes a plurality of solder bump pads.

18. The semiconductor die of claim 15, wherein said interconnect region includes a plurality of bond pads.

19. The semiconductor die of claim 15, wherein said passive circuit comprises a diplexer.

20. The semiconductor die of claim 19, wherein said at least one active device comprises an RF switch, wherein said at least one through-wafer via electrically connects said RF switch to said diplexer.