MULTIPLE DIE INTEGRATED CIRCUIT PACKAGE

• US 20080315382A1
• Filed: 09/03/2008
• Published: 12/25/2008
• Est. Priority Date: 11/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Wallace, Robert F.
• Granted Patent: US 7,939,920 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A multiple die package and removable storage card is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be electrically coupled via anisotropically conductive areas of the leadframes.

Claims

1. A removable storage card, comprising:

an insulator layer formed of an anisotropically conductive material and having a first surface and a second surface opposing the first;

a first leadframe at least partially overlying said insulator layer and at least one lead of said leadframe overlying at least one through-hole via in said insulator layer;

a second leadframe at least partially overlying the second surface of said insulator layer;

a first integrated circuit electrically coupled to at least one lead of said first leadframe;

a second integrated circuit electrically coupled to at least one lead of said second leadframe;

the first and second leadframes being electrically connected by an electrical connection formed between the first and second leadframes by causing the anisotropically conductive material in the insulator to become electrically conductive at selected locations, whereby the first and second integrated circuits are coupled electrically.

2. The removable storage card of claim 1, wherein the anisotropically conductive material becomes electrically conductive at selected locations upon application of at least one pressure, heat or other energy.

3. The removable storage card of claim 1, wherein the anisotropically conductive material becomes electrically conductive in a direction substantially orthogonal to a plane of the insulating material in the selected locations.

4. The removable storage card of claim 1, wherein said first integrated circuit comprises a controller device.

5. The removable storage card of claim 1, wherein said second integrated circuit comprises a nonvolatile memory device.

6. The removable storage card of claim 1, wherein said second integrated circuit comprises a stacked arrangement of nonvolatile memory devices.

7. The removable storage card of claim 1, wherein the first and second integrated circuits comprise non-volatile memory devices.

8. The removable storage card of claim 1, wherein the package further comprises an encapsulant at least partially encapsulating said insulator layer, said first and second integrated circuits, and said first and second leadframes.

9. The removable storage card of claim 1, wherein said first and second integrated circuits are electrically coupled to the first and second leadframes, respectively, by bond wires.

10. The removable storage card of claim 1, wherein said first and second integrated circuits are electrically coupled to said first and second leadframes, respectively, by flip chip connection.

11. The removable storage card of claim 1, wherein said first and second integrated circuits are in back-to-back relation.

12. The removable storage card of claim 1, wherein said first and second integrated circuits are in face-to-face relation.

13. A semiconductor package, comprising:

an insulator layer formed of selected locations of anisotropically conductive material, the anisotropically conductive material being conductive in the vertical direction upon application of energy, and the anisotropically conductive material being electrically insulative in the absence of the applied energy, the insulator layer further including a first surface and a second surface opposing the first;

a first leadframe at least partially overlying said insulator layer and at least one lead of said leadframe overlying at least one through-hole via in said insulator layer;

a second leadframe at least partially overlying the second surface of said insulator layer;

a first integrated circuit electrically coupled to at least one lead of said first leadframe;

a second integrated circuit electrically coupled to at least one lead of said second leadframe;

the first and second leadframes being electrically connected by an electrical connection formed between the first and second leadframes upon the anisotropically conductive material becoming electrically conductive at selected locations, whereby the first and second integrated circuits are coupled electrically.

14. The semiconductor package of claim 13, wherein the energy is at least one of heat and pressure.

15. The semiconductor package of claim 13, wherein said first integrated circuit comprises a controller device.

16. The semiconductor package of claim 13, wherein said second integrated circuit comprises a nonvolatile memory device.

17. The semiconductor package of claim 13, wherein the first and second integrated circuits comprise non-volatile memory devices.

18. The semiconductor package of claim 13, wherein the package further comprises an encapsulant at least partially encapsulating said insulator layer, said first and second integrated circuits, and said first and second leadframes.