THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USING TWO-DIMENSIONAL FABRICATION

• US 20080315407A1
• Filed: 06/20/2008
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Abandoned Application

• Current Assignee: Vertical Circuits Solutions, Inc.
• Original Assignee: Vertical Circuits LLC
• Inventors: Andrews, Lawrence Douglas JR., Caskey, Terrence, Du, Yong, McGrath, Scott, McElrea, Simon J.S.
• Application Number:
  US12/143,157
• Publication Number:
  US 20080315407A1
• Time in Patent Office: Days
• US Class Current: 257/735
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08238 the bonding area connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/31 Structure, shape, material or disposition of the layer connectors after the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g., die-to-substrate); and assemblies including a stack of at least two such devices interconnected die-to-die, or such a stack of devices electrically interconnected to underlying circuitry. Also, apparatus and methods for testing such a die.

Claims

1. A stackable integrated circuit device, including an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die and a back side edge at the conjunction of back side of the die and the sidewall, the die comprising a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die.

2. The device of claim 1 wherein the conductive trace further extends over the sidewall.

3. The device of claim 1 wherein the conductive trace further extends over the back side edge of the die and over the back side of the die.

4. The device of claim 1, further comprising a trace at the back side of the die.

5. The device of claim 4 wherein the backside trace extends over the back side edge.

6. The device of claim 1 wherein the die has a chamfered edge at the conjunction of the front side of the die and a sidewall of the die, and wherein the conductive trace extends over the chamfer at the chamfered edge of the die.

7. The device of claim 6 wherein the conductive trace further extends over the sidewall.

8. The device of claim 6 wherein the die has chamfered edge at the conjunction of the back side of the die and a sidewall of the die, and wherein the conductive trace extends over the back edge chamfer.

9. The device of claim 8, further comprising a conductive trace at the back side of the die.

10. The device of claim 9 wherein the backside trace extends over the back edge chamfer.

11. The device of claim 1 wherein the die includes both a front edge chamfer and a back edge chamfer at one of more of the sidewalls, and a conductive trace which is electrically connected to an interconnect pad extends over the front edge chamfer, the sidewall, the back edge chamfer and the die backside.

12. The device of claim 1 wherein the die further comprises an electrical insulation between the conductive trace and the die edge.

13. The device of claim 1 wherein the die further comprises an electrical insulation between the conductive trace and the die sidewall.

14. The device of claim 1 wherein the interconnect pad is one of a row of pads arranged near a centerline of the die.

15. The device of claim 1 wherein the interconnect pad is one of a row of pads arranged near an edge of the die.

16. The device of claim 15 wherein the conductive trace extends to a die edge that is parallel to the row of pads.

17. The device of claim 15 wherein the conductive trace extends to a die edge other than a die edge that is parallel to the row of pads.

19. A method for testing a stackable integrated circuit device as in claim 1, comprising providing a test socket comprising an electrically insulative base and electrically conductive contacts, wherein each contect is arranged to make electrical contact with a portion of the conductive trace at the chamfer, and wherein the contacts are connected to test circuitry, moving the device toward the test socket so that the contacts make electrical contact with respective traces at the chamfer;

and activating the test circuitry.

30. An assembly comprising a stack of devices as in claim 1, interconnected die-to-die by a conductive element that is electrically connected to the conductive trace on at least two of the stacked die.

31. An assembly comprising a stack of devices as in claim 1, interconnected to underlying circuitry on a support by a conductive element that is electrically connected to the conductive trace on at least one of the stacked die and to a site on the underlying circuitry.

18. A test socket for testing a stackable integrated circuit device as described above, comprising an electrically insulative base and electrically conductive contacts, wherein each contect is arranged to make electrical contact with a portion of the conductive trace at the chamfer, and wherein the contacts are connected to test circuitry.

20. A method for making a stackable integrated circuit device, comprising:

providing a wafer including a plurality of semiconductor die each having edges bounded by saw streets and each having an interconnect pad on an active (front) side;

forming a trench in the street, the trench defining die edges and die sidewalls; and

forming an electrically conductive trace that is electrically connected to the pad and that extends to one of the edges.

21. The method of claim 20, further comprising forming an electrical insulation between the conductive trace and the die edge.

22. The method of claim 20 wherein the trench has a generally rectangular sectional profile, so that the resulting die sidewalls are generally perpendicular to the plane of the die front side.

23. The method of claim 22 wherein the trench has a generally trapezoidal sectional profile, so that an inside angle formed at the conjunction of the die front side and the resulting sidewalls is greater than about 90°

.

24. The method of claim 20 wherein forming the electrically conductive trace comprises forming the trace to extend over the edge.

25. The method of claim 20 wherein forming the electrically conductive trace comprises forming the trace to extend over the edge and over the die sidewall.

26. The method of claim 25, further comprising forming an electrical insulation between the conductive trace and the die sidewall.

27. A method for making a stackable integrated circuit device, comprising:

providing a wafer including a plurality of semiconductor die each having edges bounded by saw streets and each having an interconnect pad on an active (front) side;

forming a chamfer at a die edge;

forming an electrically conductive trace that is electrically connected to the pad and that extends over the chamfer; and

cutting the wafer to form a sidewall.

28. The method of claim 27, further comprising forming an electrically conductive sidewall trace that is electrically connected to the conductive trace over the chamfer and that extends over the sidewall.

29. The method of claim 29, further comprising forming an electrical insulation between the conductive sidewall trace and the sidewall.