Methods of post-contact back end of line through-hole via integration
First Claim
1. A method of processing a substrate comprising a semiconductor for three dimensional integrated circuits, the method comprising:
- forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor;
etching a hole for a through-hole via from the hard mask to the semiconductor using a patterned photoresist process;
removing the patterned photoresist;
using a hard mask process to etch the hole to an amount into the semiconductor;
depositing a dielectric liner to electrically isolate the hole from the semiconductor;
depositing a gapfill metal to fill the hole; and
planarizing the surface of the substrate to the hard mask.
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Abstract
Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
62 Citations
37 Claims
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1. A method of processing a substrate comprising a semiconductor for three dimensional integrated circuits, the method comprising:
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forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor; etching a hole for a through-hole via from the hard mask to the semiconductor using a patterned photoresist process; removing the patterned photoresist; using a hard mask process to etch the hole to an amount into the semiconductor; depositing a dielectric liner to electrically isolate the hole from the semiconductor; depositing a gapfill metal to fill the hole; and planarizing the surface of the substrate to the hard mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of processing a substrate comprising a semiconductor for three dimensional integrated circuits, the method comprising:
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forming metal plug contacts through a premetal dielectric to transistors in the semiconductor; etching a hole for a through-hole via through the premetal dielectric to an amount into the semiconductor; depositing a dielectric liner to electrically isolate the hole from the semiconductor; depositing a gapfill metal to fill the hole; and planarizing the top surface of the substrate to the dielectric liner. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A microelectronic device comprising:
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at least one substrate having semiconductor transistors formed therein, the substrate having at least one hole for a through hole via; a pre-metal dielectric formed over the semiconductor transistors; a hard mask over the pre-metal dielectric; metal plugs formed through the hard mask and the pre-metal dielectric to electrically contact the transistors; a gapfill metal in the at least one hole, the gapfill metal being planarized so that the metal plugs and the gapfill metal are substantially coplanar with the top surface of the hard mask. - View Dependent Claims (34, 35, 36, 37)
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Specification