Methods of post-contact back end of line through-hole via integration

• US 20080315418A1
• Filed: 06/20/2007
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: LAM Corporation
• Original Assignee: LAM Corporation
• Inventors: Dordi, Yezdi, Redeker, Fritz, Boyd, John, Yoon, Hyungsuk Alexander, Li, Shijian
• Granted Patent: US 7,615,480 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/4763 Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28, H01L21/44
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Claims

1. A method of processing a substrate comprising a semiconductor for three dimensional integrated circuits, the method comprising:

forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor;

etching a hole for a through-hole via from the hard mask to the semiconductor using a patterned photoresist process;

removing the patterned photoresist;

using a hard mask process to etch the hole to an amount into the semiconductor;

depositing a dielectric liner to electrically isolate the hole from the semiconductor;

depositing a gapfill metal to fill the hole; and

planarizing the surface of the substrate to the hard mask.

2. The method of claim 1, further comprising depositing a diffusion barrier for the gapfill metal.

3. The method of claim 1, wherein forming the metal plugs is accomplished by deposition and planarization of copper or deposition and planarization of tungsten.

4. The method of claim 1, wherein the hard mask comprises silicon carbide or silicon carbon nitride.

5. The method of claim 1, wherein depositing the dielectric liner is accomplished by deposition of aluminum oxide.

6. The method of claim 1, wherein depositing the dielectric liner is accomplished by deposition of tetraethyl ortho silicate oxide.

7. The method of claim 1, wherein depositing the dielectric liner is accomplished by deposition of carbon doped glass, silicon carbide, or silicon carbon nitride,

8. The method of claim 2, wherein depositing the diffusion barrier is accomplished by deposition of tantalum.

9. The method of claim 2, wherein depositing the diffusion barrier is accomplished by deposition of tantalum and deposition of tantalum nitride.

10. The method of claim 2, wherein depositing the diffusion barrier is accomplished by deposition of ruthenium and deposition of tantalum nitride.

11. The method of claim 2, wherein depositing the diffusion barrier is accomplished by atomic layer deposition of ruthenium and atomic layer deposition of tantalum nitride.

12. The method of claim 2, wherein depositing the gapfill metal is accomplished by electroless deposition of copper or electrochemical plating of copper.

13. The method of claim 1, further comprising sealing the top surface of the planarized gapfill metal.

14. The method of claim 1, wherein the gapfill metal comprises copper and further comprising sealing the top surface of the planarized gapfill metal with silicon carbide, silicon carbon nitride, or cobalt tungsten boron phosphide.

15. The method of claim 1, further comprising performing one or more back end of line process steps to form one or more metallization levels to interconnect the transistors.

16. The method of claim 1, further comprising performing one or more back end of line process steps to form one or more metallization levels so as to interconnect the transistors and etching vias to the same depth to contact the metal plugs and to contact the gapfill metal in the hole.

17. A three dimensional integrated circuit having one or more substrates processed according to the method of claim 1.

18. A method of processing a substrate comprising a semiconductor for three dimensional integrated circuits, the method comprising:

forming metal plug contacts through a premetal dielectric to transistors in the semiconductor;

etching a hole for a through-hole via through the premetal dielectric to an amount into the semiconductor;

depositing a dielectric liner to electrically isolate the hole from the semiconductor;

depositing a gapfill metal to fill the hole; and

planarizing the top surface of the substrate to the dielectric liner.

19. The method of claim 18, further comprising depositing a diffusion barrier for the gapfill metal.

20. The method of claim 18, wherein depositing the dielectric liner is accomplished by deposition of aluminum oxide.

21. The method of claim 18, wherein depositing the dielectric liner is accomplished by deposition of carbon doped glass or tetraethyl ortho silicate oxide.

22. The method of claim 18, wherein depositing the dielectric liner is accomplished by deposition of silicon carbide.

23. The method of claim 18, wherein depositing the dielectric liner is accomplished by deposition of silicon carbon nitride.

24. The method of claim 19, wherein depositing the diffusion barrier is accomplished by deposition of tantalum.

25. The method of claim 19, wherein depositing the diffusion barrier is accomplished by deposition of tantalum and deposition of tantalum nitride.

26. The method of claim 19, wherein depositing the diffusion barrier is accomplished by deposition of ruthenium and deposition of tantalum nitride.

27. The method of claim 19, wherein depositing the diffusion barrier is accomplished by atomic layer deposition of ruthenium and atomic layer deposition of tantalum nitride.

28. The method of claim 18, wherein depositing the gapfill metal is accomplished by electroless deposition of copper or electrochemical plating of copper.

29. The method of claim 18, further comprising sealing the top surface of the planarized gapfill metal.

30. The method of claim 18, wherein the gapfill metal comprises copper and further comprising sealing the top surface of the planarized gapfill metal with silicon carbide, silicon carbon nitride, or cobalt tungsten boron phosphide.

31. The method of claim 18, further comprising performing one or more back end of line process steps to form one or more metallization levels to interconnect the transistors.

32. A three dimensional integrated circuit having one or more substrates processed according to the method of claim 18.

33. A microelectronic device comprising:

at least one substrate having semiconductor transistors formed therein, the substrate having at least one hole for a through hole via;

a pre-metal dielectric formed over the semiconductor transistors;

a hard mask over the pre-metal dielectric;

metal plugs formed through the hard mask and the pre-metal dielectric to electrically contact the transistors;

a gapfill metal in the at least one hole, the gapfill metal being planarized so that the metal plugs and the gapfill metal are substantially coplanar with the top surface of the hard mask.

34. The microelectronic device of claim 33, wherein the substrate comprises a silicon wafer, the gapfill metal comprises copper, the metal plugs comprise copper, and the hard mask comprises silicon carbide or silicon carbon nitride.

35. The microelectronic device of claim 33, wherein the substrate comprises a silicon wafer, the gapfill metal comprises copper, the metal plugs comprise tungsten, and the hard mask comprises silicon carbide or silicon carbon nitride.

36. The microelectronic device of claim 33, further comprising a dielectric liner substantially surrounding the gapfill metal.

37. The microelectronic device of claim 33, further comprising a diffusion barrier for the gapfill metal substantially surrounding the gapfill metal.