WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

• US 20080315434A1
• Filed: 06/19/2008
• Published: 12/25/2008
• Est. Priority Date: 06/19/2007
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.), Vertical Circuits Solutions, Inc.
• Original Assignee: Vertical Circuits LLC
• Inventors: Pan, Weiping, Crane, Scott Jay, Andrews, Lawrence Douglas JR., Caskey, Terrence, Co, Reynaldo, Melcher, DeAnn Eileen, Du, Yong, McGrath, Scott, Villavicencio, Grant, McElrea, Simon J.S., Liu, Zongrong
• Granted Patent: US 7,923,349 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 Epoxy resin
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Claims

1. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

cutting the wafer to form die edges and die sidewalls (on at least some edges) prior to thinning the wafer to the eventual die thickness; and

applying a conformal coating to the front side of the wafer.

2. The method of claim 1, further comprising

applying a die attach film to the back side of the wafer.

3. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

cutting the wafer front side on all streets to form grooves to a depth greater than a die thickness;

applying a conformal coating to the front side and the grooves; and

thinning the wafer to the die thickness.

4. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

cutting the wafer front side on streets that are fronted by interconnect margins to a depth greater than a die thickness to form die edges and sidewalls;

cutting the wafer front side on streets that are not fronted by interconnect margins to a depth less than the eventual die thickness to form die edges and a part of die sidewalls;

applying a conformal coating to the front side, the die edges, the sidewalls and the part sidewalls;

thinning the wafer to the die thickness; and

cutting through the wafer on streets that are not fronted by interconnect margins.

5. The method of claim 4, further comprising, prior to cutting through the wafer on streets that are not fronted by interconnect margins,

cutting openings through the conformal coating between the die.

6. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

cutting the wafer front side on streets that are fronted by interconnect margins to a depth greater than a die thickness to form die edges and sidewalls;

cutting the wafer front side on streets that are not fronted by interconnect margins to a depth less than the eventual die thickness to form die edges and a part of die sidewalls;

applying a conformal coating to the front side, the die edges, the sidewalls and the part sidewalls;

thinning the wafer to the die thickness;

applying a die attach film to the wafer backside; and

cutting through the wafer on streets that are not fronted by interconnect margins.

7. The method of claim 6, further comprising, prior to cutting through the wafer on streets that are not fronted by interconnect margins, cutting through the die attach film on streets that are fronted by interconnect margins.

8. The method of claim 7 wherein cutting through the die attach film and cutting the wafer front side on streets that are fronted by interconnect margins are carried out in a continuous operation.

9. The method of claim 7 wherein cutting through the die attach film and cutting the wafer front side on streets that are fronted by interconnect margins are carried out sequentially.

10. The method of claim 7, further comprising, subsequent to cutting through the wafer on streets that are not fronted by interconnect margins, cutting through the die attach film on streets that are not fronted by interconnect margins.

11. The method of claim 10 wherein cutting through the die attach film and cutting the wafer front side on streets that are not fronted by interconnect margins are carried out in a continuous operation.

12. The method of claim 10 wherein cutting through the die attach film and cutting the wafer front side on streets that are not fronted by interconnect margins are carried out sequentially.

13. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

thinning the wafer to a die thickness;

cutting through the wafer on all streets to form die edges and a part of die sidewalls;

and applying a conformal coating the front side, the die edges, and the sidewalls.

14. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

thinning the wafer to a die thickness;

cutting through the wafer on streets that are fronted by interconnect margins to form die edges and sidewalls;

cutting the wafer front side on streets that are not fronted by interconnect margins to a depth less than the die thickness to form die edges and a part of die sidewalls;

applying a conformal coating to the front side, the die edges, the sidewalls and the part sidewalls; and

cutting through the wafer on streets that are not fronted by interconnect margins.

15. A semiconductor wafer, having a front side in which semiconductor chip active regions are formed, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof, the wafer further having trenches at the active side between active regions of chips, and having an electrically insulative conformal coating over at least the interconnect margins at the active surface and the trench surfaces.

16. The wafer of claim 15 wherein the trenches that are fronted by interconnect margins of the die have a depth in the wafer at least as great as a die thickness, and the trenches that are not fronted by interconnect margins of the die have a depth in the wafer less than a die thickness.

17. A semiconductor die having a front side and a back side, and interconnect pads arranged in an interconnect margin in the front side along an interconnect edge thereof, and comprising an electrically insulative conformal coating over at least the interconnect margin and sidewalls adjacent thereto.

18. The die of claim 17, further comprising an electrically insulative film over the die backside.

19. An assembly comprising a stack of die as in claim 17, electrically interconnected die-to-die.

20. An assembly comprising a stack of die as in claim 17, electrically interconnected to underlying circuitry on a support.

21. A method for making a passivated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

thinning the wafer to a die thickness;

cutting through the wafer on streets that are fronted by interconnect margins to form die edges and sidewalls;

applying a conformal coating to the front side, the die edges and the sidewalls; and

cutting through the wafer on streets that are not fronted by interconnect margins.

22. The method of claim 21, further comprising, prior to applying the conformal coating

cutting the wafer front side on streets that are not fronted by interconnect margins to a depth less than the die thickness to form die edges and a part of die sidewalls;

wherein applying the conformal coating further comprises applying the conformal coating to the part sidewalls.