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DIGITAL PHASE LOCKED LOOP WITH DITHERING

  • US 20080315928A1
  • Filed: 05/02/2008
  • Published: 12/25/2008
  • Est. Priority Date: 06/22/2007
  • Status: Active Grant
First Claim
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1. A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:

  • a frequency reference input for receiving a reference clock;

    a controllable oscillator for generating a radio frequency (RF) clock;

    a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator; and

    a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference signal.

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