DIGITAL PHASE LOCKED LOOP WITH DITHERING
First Claim
1. A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:
- a frequency reference input for receiving a reference clock;
a controllable oscillator for generating a radio frequency (RF) clock;
a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator; and
a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference signal.
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Accused Products
Abstract
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
98 Citations
25 Claims
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1. A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:
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a frequency reference input for receiving a reference clock; a controllable oscillator for generating a radio frequency (RF) clock; a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator; and a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An analog to digital conversion system comprising:
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an input circuit for receiving an analog signal; a quantizer coupled to said input and operational to provide quantized digital samples of the analog signal; a processor coupled to the quantizer being operational to receive and process said quantized digital samples; and a dither circuit coupled to said input circuit, said dither circuit operable to generate a short sequence dither signal to perturb quantization of said analog signal. - View Dependent Claims (12, 13)
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14. A method of improving the quantized resolution of a time to digital converter (TDC), comprising:
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generating a digital short sequence dithering signal; edge dithering a reference clock signal in accordance with said short sequence dithering to form a dithered reference clock signal; and using said dithered reference clock signal by said time to digital converter to produce an output signal having a randomization of the instantaneous value of a timing difference generated by said time to digital converter. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A cellular telephone comprising:
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a reference frequency generator for forming a reference clock; a transmitter connected to receive the reference clock, comprising; a phase locked loop (PLL), wherein the PLL comprises; a controllable oscillator for generating a radio frequency (RF) clock; phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator; a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference signal; and a data modulating input for providing data deviation commands operable to adjust the frequency of the controllable oscillator thereby providing frequency modulation of the local oscillator.
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Specification