METHODS FOR INTEGRATION OF THIN-FILM CAPACITORS INTO THE BUILD-UP LAYERS OF A PRINTED WIRING BOARD

• US 20080316723A1
• Filed: 06/19/2007
• Published: 12/25/2008
• Est. Priority Date: 06/19/2007
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Borland, William, Dietz, Karl Hartmann, Amey, Daniel Irwin JR., Palanduz, Cengiz Ahmet, Erickson, J. Stan
• Granted Patent: US 7,841,075 B2
• Time in Patent Office: Days
• US Class Current: 361/763
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0175 Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/09481 Via in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09518 Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
• CPC Class Codes: H05K 2201/09718 Clearance holes
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 2203/1126 Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents
• CPC Class Codes: H05K 3/1291 Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base

Abstract

Provided herein are devices comprising a printed wiring board that comprise, singulated capacitors fabricated from known good, thin-film, fired-on-foil capacitors. Provided are methods of incorporating the singulated capacitors into the build-up layers of a printed wiring board to minimize impedance. The singulated capacitors have a pitch that allows each power and ground terminal of an IC to be directly connected to a power and ground electrode, respectively, of its own singulated capacitor. Using a feedstock of known good, fired-on-foil capacitors allows for improved PWB yield.

Claims

1. A device comprising a printed wiring board,

the printed wiring board supporting

an integrated circuit that has

an area,

a plurality of active power and ground terminals, and

a plurality of signal terminals,

the printed wiring board comprising:

a plurality of known good, singulated capacitors,

each known good, singulated capacitor

having a power electrode and a ground electrode, and

being formed from a known good, thin-film, fired-on-foil capacitor,

the known good, thin-film, fired-on-foil capacitor comprising

a first and second electrode,

the second electrode having a footprint,

wherein each known good, singulated capacitor is formed within the footprint of the second electrode of the known good, fired-on-foil capacitor and embedded into the build-up layers of the printed wiring board;

wherein each known good, singulated capacitor is of a size and of a pitch such that the plurality of singulated capacitors lies directly under and within the area of the IC;

wherein each active power and ground terminal of the IC is directly connected to a corresponding power and ground electrode, respectively, of a known good, singulated capacitor; and

wherein each signal terminal of the IC is directly connected to a signal pad isolated from the singulated capacitors but formed at the same time from the known good fired-on-foil capacitor.

2. The device of claim 1, wherein the dielectric layer of each singulated capacitor is a high K thin-film ceramic selected from materials comprising the general formula ABO₃ selected from the group BaTiO₃;

BaSrTiO₃;

PbTiO₃;

CaTiO₃;

PbZrO₃;

BaZrO₃ and SrZrO₃or mixtures thereof.

3. The device of claim 1, wherein the foil of the known good, fired-on-foil capacitors is selected from the group consisting of nickel, nickel alloys, copper, copper alloys, copper-invar-copper, invar, nickel-coated copper and any combination of these.

4. The device of claim 1, wherein the dielectric layer has been fired at an elevated temperature under a protective atmosphere.

5. The device of claim 1, wherein the printed wiring board comprises singulated capacitors formed from at least one known good component diced from a foil containing known good, fired-on-foil capacitors, the known good component comprising at least one known good, fired-on-foil capacitor.

6. The device of claim 5, wherein the known good components have been placed onto a build-up layer of the printed wiring board by pick and place techniques.

7. The device of claim 6, wherein the known good components were sorted prior to placement onto the build-up layer and placed thereon according to their capacitance tolerance or other electrical property.

8. The device of claim 1, further comprising a carrier film applied to the side of the foil structure containing the fired-on-foil capacitor.

29. The device of claim 1, wherein the plurality of singulated capacitors is embedded in the at least one build-up layer of a PWB that is connected to the terminals of the IC by a via having a length less than 100 microns and an inductance less than 20 pico-Henries.

9. A method of making a device comprising a printed wiring board, the method comprising:

providing at least one foil structure having

two sides and comprising

a known good, thin-film, fired-on-foil capacitor comprising

a dielectric layer and

a second electrode layer having a footprint;

applying metal to the side of the foil structure containing the second electrode;

patterning the side of the foil structure not containing the second electrode,

thereby forming a plurality of first electrodes;

laminating the patterned side of the foil structure to a build-up layer of a printed wiring board;

patterning the side of the foil structure containing the second electrode of the fired-on-foil capacitor,

thereby forming a plurality of second electrodes within the footprint of the second electrode layer,

whereby the forming of the plurality of the first electrodes and of the plurality of the second electrodes forms a plurality of singulated capacitors of a certain size and pitch so that each singulated electrode may be directly attached to a terminal of an IC; and

wherein the plurality of singulated capacitors lies directly under and within the area of the integrated circuit.

11. The method of claim 9, wherein interconnecting comprises forming and plating vias.

13. The method of claim 9, wherein the entire area of the dielectric layer is supported.

15. The method of claim 9, wherein the etched side of the foil structure not containing the fired-on-foil capacitor is laminated to other PWB layers, thereby creating a coreless multilayer structure either in a single lamination step wherein multiple layers are laminated together in unison, or in multiple lamination steps wherein each layer is laminated individually.

17. The method of claim 9, further comprising:

testing the fired-on-foil capacitor to determine that it has the quality of known good by its capacitance tolerance and/or other electrical characteristic.

20. The method of claim 17, further comprising:

sorting the diced component derived from the known good, fired-on-foil capacitor by its capacitance tolerance or other electrical property; and

incorporating the diced component into the build-up layer according to its capacitance tolerance or other electrical property.

21. The method of claim 9, further comprising:

before patterning, applying a carrier film to the side of the foil structure containing a capacitor.

23. A method of making a printed wiring board comprising the method of claim 9.

25. The printed wiring board made by the method of claim 9.

27. A method of incorporating into a build-up layer of a printed wiring board a singulated capacitor comprising the method of claim 9.

10. A method of making a device comprising a printed wiring board, the method comprising:

providing at least one foil structure having

two sides and comprising

a known good, thin-film, fired-on-foil capacitor comprising

a dielectric layer and

a second electrode layer having a footprint;

applying metal to the side of the foil structure containing the second electrode;

patterning the side of the foil structure not containing the second electrode;

thereby forming a plurality of first electrodes;

dicing the foil structure to form known good, diced components,

the known good, diced components comprising at least one fired-on-foil capacitor;

picking and placing onto a build-up layer of the printed wiring board at least one diced component so that the patterned side of the component contacts the build-up layer;

laminating at least one known good, diced component to the build-up layer;

patterning the side of the foil structure containing the second electrode of the fired-on foil capacitor,

thereby forming a plurality of second electrodes within the footprint of the second electrode layer,

whereby the forming of the plurality of the first electrodes and of the plurality of the second electrodes forms a plurality of singulated capacitors of a certain size and pitch so that each singulated electrode may be directly attached to a terminal of an IC; and

wherein the plurality of singulated capacitors lies directly under and within the area of the integrated circuit.

12. The method of claim 10, wherein interconnecting comprises forming and plating vias.

14. The method of claim 10, wherein the entire area of the dielectric layer is supported.

16. The method of claim 10, wherein the etched side of the foil structure not containing the fired-on-foil capacitor is laminated to other PWB layers, thereby creating a coreless multilayer structure either in a single lamination step wherein multiple layers are laminated together in unison, or in multiple lamination steps wherein each layer is laminated individually.

18. The method of claim 10, further comprising:

testing the fired-on-foil capacitor to determine that it has the quality of known good by its capacitance tolerance and/or other electrical characteristic.

19. The method of claim 16, further comprising:

identifying the known bad, fired-on-foil capacitor; and

preventing assembly of components to the printed wiring board containing the known bad, fired-on-foil capacitor.

22. The method of claim 10, further comprising:

before patterning, applying a carrier film to the side of the foil structure containing a capacitor.

24. A method of making a printed wiring board comprising the method of claim 10.

26. The printed wiring board made by the method of claim 10.

28. A method of incorporating into a build-up layer of a printed wiring board a singulated capacitor comprising the method of claim 10.