Method of making high forward current diodes for reverse write 3D cell

• US 20080316796A1
• Filed: 06/25/2007
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad
• Granted Patent: US 7,684,226 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Claims

1. A method of making a nonvolatile memory device, comprising:

forming a first electrode;

forming at least one nonvolatile memory cell comprising a diode and a metal oxide antifuse dielectric layer over the first electrode; and

forming a second electrode over the at least one nonvolatile memory cell;

wherein in use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

2. The method of claim 1, wherein the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes.

3. The method of claim 2, wherein the metal oxide antifuse dielectric layer comprises at least one of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride or combinations thereof with at least one of SiO₂ or SiN_x.

4. The method of claim 3, wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide.

5. The method of claim 4, wherein the metal oxide antifuse dielectric layer is located adjacent to a p-type region of the diode.

6. The method of claim 1, further comprising patterning the diode and the metal oxide antifuse dielectric layer such that the diode and the metal oxide antifuse dielectric layer form a pillar having a substantially cylindrical shape.

7. The method of claim 1, further comprising applying a forward bias to the diode to switch the diode from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

8. The method of claim 7, wherein the application of the forward bias forms a conductive link through the metal oxide antifuse dielectric layer.

9. The method of claim 8, wherein a metal dopant diffuses from the metal oxide antifuse dielectric layer into a p-type region of the diode located adjacent to the metal oxide antifuse dielectric layer after the conductive link is formed.

10. The method of claim 1, wherein the metal oxide antifuse dielectric layer has a thickness of 10 to 100 Angstroms.

11. A method of operating a nonvolatile memory device, comprising:

providing at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer breached with a conductive link, wherein the diode has been switched from a first higher resistivity, unprogrammed state to a second lower resistivity, programmed state; and

applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state.

12. The method of claim 11, further comprising applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state.

13. The method of claim 11, further comprising sensing a resistivity state of the diode as a data state of the memory cell.

14. The method of claim 13, wherein the step of sensing comprises applying a read voltage to the memory such that the memory cell exhibits a read current of at least 3.5×

10<sup>−

5</sup> A for at least 1.5V read voltage.

15. The method of claim 11, wherein:

the diode is switched into the second, programmed state in a factory in which the memory cell is fabricated; and

the step of applying the reverse bias is performed by a user of the memory cell after the memory cell leaves the factory in which the memory cell is fabricated.

16. The method of claim 11, further comprising a conductive link which breaches the metal oxide antifuse dielectric layer.

17. The method of claim 11, wherein:

the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes; and

the metal oxide antifuse dielectric layer comprises at least one of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride or combinations thereof with at least one of SiO₂ or SiN_x.

18. The method of claim 17, wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide.

19. The method of claim 18, wherein the metal oxide antifuse dielectric layer is located adjacent to a p-type region of the diode such that during operation of the memory cell, aluminum or hafnium diffuses from the metal oxide antifuse dielectric layer into the p-type region of the diode.

20. The method of claim 11, wherein the diode and the metal oxide antifuse dielectric layer form a pillar having a substantially cylindrical shape.