Electronic Circuit With a Memory Matrix
First Claim
1. An electronic circuit, comprising a memory matrix comprising rows and columns of memory cells, the matrix comprising first row conductors for each of the rows, second row conductors for successively overlapping pairs of adjacent rows and column conductors for each of the columns, each of said memory cells comprising an access transistor, a node and a first and second resistive memory element, the access transistor having a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node, the first and second resistive memory element being coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
10 Assignments
0 Petitions
Accused Products
Abstract
An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
9 Citations
11 Claims
- 1. An electronic circuit, comprising a memory matrix comprising rows and columns of memory cells, the matrix comprising first row conductors for each of the rows, second row conductors for successively overlapping pairs of adjacent rows and column conductors for each of the columns, each of said memory cells comprising an access transistor, a node and a first and second resistive memory element, the access transistor having a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node, the first and second resistive memory element being coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
Specification