High forward current diodes for reverse write 3D cell

• US 20080316809A1
• Filed: 06/25/2007
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad
• Granted Patent: US 7,830,697 B2
• Time in Patent Office: Days
• US Class Current: 365/175
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Claims

1. A nonvolatile memory device, comprising:

at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer; and

a first electrode and a second electrode electrically contacting the at least one memory cell;

wherein in use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

2. The device of claim 1, wherein the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes.

3. The device of claim 2, wherein the metal oxide antifuse dielectric layer has a dielectric constant higher than 3.9.

4. The device of claim 2, wherein the metal oxide antifuse dielectric layer comprises at least one of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride or combinations thereof with at least one of SiO₂ or SiN_x.

5. The device of claim 4, wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide.

6. The device of claim 5, wherein the metal oxide antifuse dielectric layer is located adjacent to a p-type region of the diode.

7. The device of claim 6, wherein:

the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape, and

the p-type region of the diode contains aluminum or hafnium diffused from the antifuse dielectric layer after the cell is programmed.

8. The device of claim 1, wherein:

the memory cell comprises a read/write memory cell; and

the diode comprises a p-i-n semiconductor diode which acts as a read/write element of the memory cell.

9. The device of claim 8, wherein the memory cell comprises a rewritable memory cell.

10. The device of claim 9, wherein:

an application of a forward bias between the first and the second electrodes is adapted to form a conductive link breaching the metal oxide antifuse dielectric layer and to program the diode;

the programmed diode is adapted to be placed in a high resistivity, unprogrammed state by an application of a reverse bias to the diode; and

the diode in the high resistivity, unprogrammed state is adapted to be returned to a low resistivity, programmed state by an application of a forward bias to the diode.

11. The device of claim 1, wherein the device comprises a monolithic, three dimensional array of memory cells located over the diode.

12. A nonvolatile memory device, comprising:

a plurality of memory cells; and

a first electrode and a second electrode electrically contacting the plurality of memory cells;

wherein each memory cell of the plurality of memory cells comprises a diode and a metal oxide antifuse dielectric layer arranged in series between the first and the second electrodes, and the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape.

13. The device of claim 12, wherein the metal oxide antifuse dielectric layer comprises at least one of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium silicon oxide, aluminum silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxynitride, zirconium silicon aluminum oxide, hafnium aluminum silicon oxide, hafnium aluminum silicon oxynitride, or zirconium silicon aluminum oxynitride or combinations thereof with at least one of SiO₂ or SiN_x.

14. The device of claim 13, wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide.

15. The device of claim 14, wherein the p-type region of the diode contains aluminum or hafnium diffused from the antifuse dielectric layer after the cell is programmed.

16. The device of claim 14, wherein each memory cell provides a read current of at least 3.5×

10<sup>−

5</sup> A for at least 1.5V read voltage.

17. The device of claim 12, wherein the metal oxide antifuse dielectric layer has a thickness of 10 to 100 Angstroms.

18. The device of claim 12, wherein:

the plurality of memory cells comprise read/write memory cells; and

the diode in each of the plurality of memory cells comprises a p-i-n semiconductor diode which acts as a read/write element of each of the plurality of the memory cells.

19. The device of claim 18, wherein in use, the diode in each of the plurality of the memory cells acts as a read/write element of each of the plurality of the memory cells by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

20. The device of claim 19, wherein:

the plurality of the memory cells comprise rewritable memory cells;

an application of a forward bias between the first and the second electrodes is adapted to form a conductive link breaching the metal oxide antifuse dielectric layer and to program the diode in each of the plurality of the memory cells;

the programmed diode is adapted to be placed in a high resistivity, unprogrammed state by an application of a reverse bias to the diode; and

the diode in the high resistivity, unprogrammed state is adapted to be returned to the low resistivity, programmed state by an application of a forward bias to the diode

the metal oxide antifuse dielectric layer is adapted to be ruptured by a conductive link by an application of a forward bias between the first and the second electrodes to program the diode;

the programmed diode is adapted to be placed in a high resistivity, unprogrammed state by an application of a reverse bias to the diode having a value greater than a predetermined critical voltage value; and

the unprogrammed diode is adapted to be returned to the low resistivity, programmed state by an application of a forward bias to the diode.