SYSTEMS FOR PROGRAMMING MULTILEVEL CELL NONVOLATILE MEMORY

• US 20080316816A1
• Filed: 06/25/2007
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lin, Jason T.
• Granted Patent: US 7,630,252 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.

Claims

1. A memory system comprising:

a first block that has only two memory states per cell;

a second block that has more than two memory states per cell; and

a circuit that programs a sequence of data to the first block and in parallel programs first portions, but not second portions, of the sequence of data to the second block, thus partially programming individual cells of the second block, and subsequently further programs the cells of the second block according to the second portions of the sequence of data that are stored in the first block.

2. The memory system of claim 1 wherein the second block has sixteen memory states per cell.

3. The memory system of claim 2 wherein the programming of first portions of the sequence of data to the second block uses four of the sixteen states per cell.

4. The memory system of claim 1 wherein the first block and the second block include strings of floating gate memory cells connected in series to form NAND strings.

5. The memory system of claim 4 wherein NAND strings are connected by bit lines alternate bit lines programmed together.

6. The memory system of claim 1 wherein the first block and the second block are connected by common bit lines.

7. The memory system of claim 1 wherein the first block is on a first die and the second block is on a second die.

8. The memory system of claim 7 wherein the first die has blocks of cells that have threshold voltage ranges that are mapped to the plurality of memory states and the second die has blocks of cells that have threshold voltage ranges that are mapped to only two memory states.

9. The memory system of claim 1 wherein the first block is on a first chip and the second block is on a second chip.

10. A nonvolatile memory system comprising:

a first block that includes a first plurality of cells, each of the first plurality of cells having a threshold voltage range that is mapped to two memory states;

a second block that includes a second plurality of cells, each of the second plurality of cells having a threshold voltage range that is mapped to a plurality of memory states, the plurality of memory states including more than two memory states; and

a circuit that programs a sequence of data, consisting of first portions of data and second portions of data, to the first block and in parallel programs the first portions, but not the second portions of the sequence of data to the second block such that the second plurality of cells are programmed to fewer than all of the plurality of memory states, the circuit subsequently further programming the second plurality of cells according to the first portions and the second portions of data stored in the first block, the second plurality of cells programmed to all of the plurality of memory states by the further programming.

11. The nonvolatile memory system of claim 10 wherein the plurality of memory states consists of sixteen memory states.

12. The nonvolatile memory system of claim 11 wherein the fewer than all of the plurality of memory states consists of four memory states, the four memory states associated with lower portions of the threshold voltage range than are associated with other ones of the plurality of memory states.

13. The nonvolatile memory system of claim 10 wherein, subsequent to the further programming, additional programming steps are performed, the additional programming steps compensating for effects of charge in neighboring memory cells.