MCU WITH INTEGRATED VOLTAGE ISOLATOR AND INTEGRATED GALVANICALLY ISOLATED ASYNCHRONOUS SERIAL DATA LINK

• US 20080317106A1
• Filed: 06/30/2008
• Published: 12/25/2008
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Bresemann, David, Alfano, Donald E., Leung, Ka Y.
• Granted Patent: US 7,821,428 B2
• Time in Patent Office: Days
• US Class Current: 375/220
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4278 using an embedded synchronisation
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency.

Claims

1. An integrated circuit, comprising:

a first microcontroller unit disposed on a first die for executing instructions in accordance with a first clock frequency generated on the first die, the first microcontroller unit including a first processing core for generating parallel data in accordance with the first clock frequency;

first transceiver circuitry located on the first die for converting between the parallel data and a serial data stream in accordance with a second clock frequency generated on the first die that is faster than the first clock frequency;

a second microcontroller unit disposed on a second die for executing instructions in accordance with a third clock frequency generated on the second die, the second microcontroller unit including a second processing core for processing parallel data in accordance with the third clock frequency;

second transceiver circuitry located on the second die for converting between a serial data stream and parallel data in accordance with the fourth clock frequency generated on the second die that is faster than the third clock frequency;

the first die galvanically isolated from the first die; and

isolation circuitry for transmitting serial data from the first transceiver to the second transceiver across a galvanic isolation barrier such that parallel data processed by the first microcontroller unit can be received by the second microcontroller unit with the transmission across the galvanic isolation link being a serial data stream, and the clocks on the first die not synchronized with the clocks on the second die.

2. The integrated circuit of claim 1, further including an analog to digital converter for converting an analog signal into parallel data on the first die for processing by the first microcontroller unit.

3. The integrated circuit of claim 1, further including a digital to analog converter for converting the parallel data processed by the second microcontroller unit to an analog signal.

4. The integrated circuit of claim 1, wherein each of the first and second transceiver circuitry further comprises:

an encoder/decoder circuit for converting between a non-encoded parallel data and encoded parallel data; and

a serializer/deserializer circuit for converting between the encoded serial data and the encoded parallel data stream.

5. The integrated circuit of claim 4, wherein the encoder/decoder circuit performs Manchester encoding and decoding.

6. The integrated circuit of claim 4, further including at least one special function register associated with the second die for storing the parallel data provided by the second transceiver circuitry, wherein the at least one special function register generates an interrupt to the processing core associated with the second microcontroller unit indicating the presence of the parallel data received over the isolation link.

7. The integrated circuit of claim 4, further including a respective multiplier clock for multiplying a respective system clock on each of the respective first and second dies, each respective system clock operating in accordance with the respective first and third clock frequencies and controlling the respective encoder/decoders, the respective multiplier clocks for multiplying the respective system clocks by a respective predetermined multiplier to create the respective second and fourth clock frequencies for operating the respective serializer/deserializer circuits and the respective isolation circuitry in accordance with the second clock frequency.

8. The integrated circuit of claim 1, wherein the first microcontroller unit converts between an input analog signal and parallel data to be transmitted and the second microcontroller unit converts between received parallel data and an output analog signal.

9. The integrated circuit of claim 1, wherein the first microcontroller unit converts between data in an input data protocol and parallel data to be transmitted and the second microcontroller converts between received parallel data and output data in an output data protocol.

10. An integrated circuit, comprising:

first and second semiconductor die disposed in a package and galvanically isolated;

a galvanic isolation data link disposed between the first and second die;

a first microcontroller unit disposed on the first die for executing instructions in accordance with a first clock frequency generated on the first die, the first microcontroller unit including a first processing core for providing parallel data to be transmitted across the isolation link to the second die across, and the parallel data generated and processed in accordance with the first clock frequency;

a second microcontroller unit disposed on the second die for executing instructions in accordance with substantially the first clock frequency, the second microcontroller unit including a second processing core for processing parallel data received across the isolation link from the first die, and the received parallel data processed in accordance with the substantially the first clock frequency;

the galvanic isolation link including capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit for providing a high voltage isolation link between the first and the second microcontroller units, the capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributing a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit, the capacitive isolation circuitry further transmitting data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with respective isolation clock frequencies on each side of the isolation link

wherein the clock frequencies on either side of the isolation link operate asynchronous.

11. The integrated circuit of claim 10, further including:

first processing circuitry located on the first die for converting between the parallel data to be transmitted and the serial data stream; and

second processing circuitry located on the second die for converting between the serial data stream and the received parallel data.

12. The integrated circuit of claim 11, further including an analog to digital converter on the first die for converting an input analog signal into the parallel data to be transmitted.

13. The integrated circuit of claim 11, further including a digital to analog converter on the second die for converting the received parallel data to an output analog signal.

14. The integrated circuit of claim 11, wherein the first and second processing circuitry further comprises:

an encoder/decoder circuit for converting between non-encoded parallel data and encoded parallel data; and

a serializer/deserializer circuit for converting between the encoded serial data and the encoded parallel data.

15. The integrated circuit of claim 14, wherein the encoder/decoder circuit performs Manchester encoding and decoding.

16. The integrated circuit of claim 14, further including at least one special function register on the second die for storing the received parallel data, wherein the at least one special function register generates an interrupt to the processing core associated with the second microcontroller unit indicating the presence of the received parallel data.

17. The integrated circuit of claim 14, further including a multiplier clock on the first die for multiplying a system clock on the first die, operating in accordance with the first clock frequency and controlling the encoder/decoder, by a predetermined multiplier to create the second clock frequency for operating the serializer/deserializer circuit and the capacitive isolation circuitry in accordance with the second clock frequency.

18. The integrated circuit of claim 10, wherein the first microcontroller unit converts an input analog signal to the parallel data to be transmitted and the second microcontroller unit converts the parallel stream of data to an output analog signal.

19. The integrated circuit of claim 10, wherein the first microcontroller unit converts data in a first protocol to the parallel data to be transmitted and the second microcontroller converts the received parallel data to data in a second protocol.

21. The integrated circuit of claim 19, wherein the first and second transceiver circuitry further comprises:

an encoder/decoder circuit for converting between a non-encoded parallel data stream and an encoded parallel data stream; and

a serializer/deserializer circuit for converting between the encoded serial data and the encoded parallel data stream.

23. The integrated circuit of claim 14, further including a multiplier clock for multiplying a system clock, operating in accordance with the first clock frequency and controlling the encoder/decoder, by a predetermined multiplier to create the second clock frequency for operating the serializer/deserializer circuit and the capacitive isolation circuitry in accordance with the second clock frequency.

20. An integrated circuit, comprising:

a first microcontroller unit for executing instructions in accordance with a first clock frequency located on a first die including a first processing core for providing a parallel stream of data in accordance with the first clock frequency;

first transceiver circuitry located on the first die for converting between the parallel data stream and the serial data stream in accordance with a second clock frequency that is faster than the first clock frequency;

a second microcontroller unit for executing instructions in accordance with the first clock frequency located on a second die including a second processing core for receiving the parallel stream of data in accordance with the first clock frequency;

second transceiver circuitry located on the second die for converting between the serial data stream and the parallel data stream in accordance with the second clock frequency;

capacitive isolation circuitry for bidirectionally transmitting data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency and providing galvonic isolation between the first microcontroller unit and the second microcontroller unit.

22. The integrated circuit of claim 20, further including at least one special function register for storing the parallel data sample, wherein the at least one special function register generates an interrupt to the processing core indicating the presence of the parallel data sample.