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Method of Design Analysis of Existing Integrated Circuits

  • US 20080317328A1
  • Filed: 08/29/2008
  • Published: 12/25/2008
  • Est. Priority Date: 08/31/2004
  • Status: Active Grant
First Claim
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1. A method of determining possible locations of standard cells in an image of an IC layout comprising:

  • extracting points of interest from the image;

    creating a descriptor in the vicinity of each of the points of interest;

    extracting a first instance of a standard cell from the image;

    comparing descriptors from the first instance of a standard cell to the other the descriptors of the image to identify similar points of interest;

    casting votes on the similar points of interest to show the level of confidence on the similarity of the similar points of interest; and

    computing the weight of the votes and determining possible matches by locations on the image showing high weights.

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