METHOD FOR SELECTIVELY FORMING SYMMETRICAL OR ASYMMETRICAL FEATURES USING A SYMMETRICAL PHOTOMASK DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE

• US 20080318032A1
• Filed: 06/22/2007
• Published: 12/25/2008
• Est. Priority Date: 06/22/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zhu, Hongbin, Madsen, Jeremy
• Granted Patent: US 7,985,681 B2
• Time in Patent Office: Days
• US Class Current: 428/336
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/265 1 mil or less

Abstract

A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.

Claims

1. A method used during semiconductor device feature fabrication, comprising:

forming at least one material to be etched;

forming a plurality of first mask features at first locations and a plurality of second mask features over the material to be etched;

partially etching into the material to be etched with a first etch at second locations, and leaving the material to be etched unetched at the first locations;

removing the first mask features;

then

with the second mask features exposed, etching the material to be etched with a second etch at both the first and second locations.

2. The method of claim 1 wherein the process act of etching into the material to be etched with the first etch at second locations is performed with both the first and second mask features exposed.

3. The method of claim 1 further comprising:

etching a first volume of material from the material to be etched at the first locations to form first openings during the second etch; and

etching a second volume of material from the material to be etched at the second locations to form second openings during the first and second etches, with the second volume of material being different from the first volume of material.

4. The method of claim 3 wherein the second volume of material etched is less than the first volume of material etched.

5. The method of claim 4 further comprising forming a conductive material to fill the first and second openings, wherein a first cross sectional area of the conductive material within the first opening is different than a second cross sectional area of the conductive material within the second opening.

6. The method of claim 5 wherein the second cross sectional area is less than the first cross sectional area.

7. A method used during fabrication of a semiconductor device, comprising:

forming a plurality of mask features over a material to be etched, wherein the plurality of mask features have uniform dimensions and a regular pitch;

forming a conformal spacer material over the material to be etched and on the plurality of mask features;

etching the conformal spacer material to form a plurality of spacers, with paired spacers contacting at least a portion of each mask feature;

with the plurality of mask features and the plurality of spacers exposed, partially etching the material to be etched to form a plurality of partially etched first openings therein;

removing the plurality of mask features to form an opening between each of the paired spacers;

then

with the plurality of spacers exposed, etching the material to be etched through the opening between each of the paired spacers to form second openings within the material to be etched and further etching the partially etched first openings to form completed first openings, wherein the second openings comprise a different cross sectional profile than the completed first openings.

8. The method of claim 7 further comprising:

forming a conductive material within the second openings and within the completed first openings; and

planarizing the conductive material to remove the conductive material from over the material to be etched,

wherein a first volume of conductive material within the completed first openings is less than a second volume of conductive material within the second openings.

9. The method of claim 7 further comprising:

forming the second openings to have a rectangular profile; and

forming the completed first openings to have a “

V”

shaped profile.

10. A method used during fabrication of a semiconductor device, comprising:

forming polysilicon over a semiconductor wafer substrate assembly comprising at least a portion of a semiconductor wafer;

forming suicide on the polysilicon;

forming oxide on the silicide;

forming transparent carbon (TC) on the oxide;

forming dielectric antireflective coating (DARC) on the TC;

forming a plurality of first mask features at first locations and a plurality of second mask features over the DARC;

with both the first and second mask features exposed, etching the DARC using an isotropic etch and stopping the etch when the TC is exposed;

removing the first mask features;

then

with the second mask features exposed, etching the TC at the first location and stopping on or in the oxide to form a first opening while etching the DARC, the TC, the oxide and the silicide at a second location and stopping on or in the polysilicon to form a second opening.

11. The method of claim 10 further comprising:

etching a first volume of material from the DARC and the TC to form the first opening; and

etching a second volume of material from the DARC, the TC, the oxide, and the silicide to form the second opening, wherein the second volume is greater than the first volume.

12. The method of claim 11 further comprising forming a conductive material to fill the first and second openings, wherein a first cross sectional area of the conductive material within the first opening is less than a second cross sectional area of the conductive material within the second opening.

13. The method of claim 11 wherein the semiconductor device is a NAND flash device and the method further comprises:

forming the polysilicon to a thickness of about 750 Å

;

forming the silicide to a thickness of about 900 Å

;

forming the oxide to a thickness of about 1,400 Å

;

forming the TC to a thickness of about 2,000 Å

; and

forming the DARC to a thickness of from about 200 Å

to about 360 Å

.

14. A method for forming asymmetrical semiconductor device features, comprising:

forming a material to be etched;

forming a patterned mask having a plurality of symmetrical features over the material to be etched;

forming a spacer material over the plurality of symmetrical features;

etching the spacer material to form a plurality of spacers, with two cross sectional spacers contacting at least a portion of the plurality of symmetrical features;

with the spacers and the patterned mask exposed, etching the material to be etched at a plurality of first locations, while a plurality of second locations remain unetched;

removing the patterned mask;

then

with the spacers exposed, etching the material to be etched at the plurality of first locations and at the plurality of second locations to result in the material to be etched comprising first etched features at the first location having a first cross sectional profile and second etched features at the second location having a second cross section different from the first cross section.

15. The method of claim 14 further comprising forming the material to be etched using a method comprising:

forming a tungsten silicide material;

forming a tetraethyl orthosilicate glass material on the tungsten suicide material;

forming a transparent carbon material on the tetraethyl orthosilicate glass material; and

forming a dielectric antireflective coating on the transparent carbon material.

16. The method of claim 15 further comprising forming the tungsten silicide material on a polysilicon material.

17. The method of claim 14 further comprising:

forming a conformal conductive material within the first etched features, within the second etched features, and over the material to be etched; and

removing the conformal conductive material from over the material to be etched, wherein subsequent to removing the conformal conductive material from over the material to be etched the first and second etched features remain filled with conductive material.

18. A structure, comprising:

a structure to be etched, comprising;

a polysilicon material;

a tungsten silicide material overlying the polysilicon material;

a dielectric material overlying the tungsten silicide material;

a transparent carbon (TC) material overlying the dielectric material; and

an antireflective material overlying the TC material; and

a plurality of paired cross sectional mask material spacers overlying the antireflective material.

19. The structure of claim 18, further comprising:

the polysilicon material being about 750 angstroms (Å

) thick and contacting the tungsten suicide material;

the tungsten silicide material being about 900 Å

thick and contacting the dielectric material;

the dielectric material being a tetraethyl orthosilicate (TEOS) material about 1,400 Å

thick and contacting the TC material;

the transparent carbon layer being about 2,000 Å

thick and contacting the antireflective material; and

the antireflective material being a deposited antireflective coating (DARC) from about 200 Å

to about 260 Å

thick.

20. The structure of claim 19 further comprising:

the plurality of paired cross sectional mask material spacers having a uniform distance between adjacent paired spacers and between adjacent pairs of spacers, wherein the distance between adjacent paired spacers is about equal to the distance between adjacent pairs of spacers;

a plurality of first openings at a level below the plurality of paired cross sectional mask material spacers, with one first opening located between each paired spacer; and

a plurality of second openings at a level below the plurality of paired cross sectional mask material spacers, with one second opening located between each pair of spacers,

wherein a volume of each first opening is substantially less than a volume of each second opening.