METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

• US 20080318361A1
• Filed: 07/13/2007
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Sung Min, KIM, Jong Hoon, YANG, Seung Taek, KIM, Seong Cheol, SUH, Min Suk, HAN, Kwon Whan, LEE, Seung Hyun, PARK, Chang Jun, LEE, Ha Na
• Granted Patent: US 7,795,139 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Claims

1. A method for manufacturing a semiconductor chip for packaging, comprising the steps of:

forming a groove having a side wall on the upper surface of a semiconductor chip having a bonding pad on the upper surface thereof, wherein the groove is closer to the outer perimeter of the semiconductor chip upper surface than the bonding pad;

forming an insulation layer on the side wall of the groove;

forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer;

etching the metal layer to simultaneously form a through silicon via filled with metal in the groove and a distribution layer for connecting the through silicon via to the bonding pad; and

removing a portion of the lower surface of the semiconductor chip to reduce the thickness thereof such that the a part of the through silicon via at the bottom of the groove protrudes out of the lower surface of the semiconductor chip.

2. The method for manufacturing a semiconductor chip for packaging according to claim 1, further comprising the step of:

after removing a portion of the lower surface of the semiconductor chip to reduce the thickness thereof, forming mold parts on the upper and lower surfaces of the semiconductor chip excluding the through silicon via that remains exposed on the upper and lower surfaces of the semiconductor chip formed with mold parts.

3. The method for manufacturing a semiconductor chip for packaging according to claim 1, wherein the step of forming the metal layer comprises the steps of:

depositing a seed metal layer over the semiconductor chip including the groove;

plating the metal layer over the seed metal layer; and

etching back the metal layer to reduce the thickness thereof.

4. The method for manufacturing a semiconductor chip for packaging according to claim 3, wherein each of the seed metal layer and the metal layer comprises any one of:

copper (Cu), aluminum (Al), gold (Au), and an alloy repectively thereof.

5. The method for manufacturing a semiconductor chip for packaging according to claim 1, wherein the step of simultaneously forming the through silicon via and the distribution layer comprises the steps of:

forming a mask over an area of the metal layer in which the through silicon via and the distribution layer are to be formed;

etching the portion of the metal layer not covered by the mask; and

removing the mask.

6. The method for manufacturing a semiconductor chip for packaging according to claim 5, wherein the etching of the metal layer is carried out in a wet etching process.

7. The method for manufacturing a semiconductor chip for packaging according to claim 1, wherein the step of removing the lower surface of the semiconductor chip is carried out in at least one of a grinding process and an etching process.

8. The method for manufacturing a semiconductor chip for packaging according to claim 1, wherein every step of claim 1 is performed to a semiconductor chip at a wafer level.

9. The method for manufacturing a semiconductor chip for packaging according to claim 8, further comprising the step of:

after performing the step of removing a portion of the lower surface of the semiconductor chip, sawing the wafer so as to separate the semiconductor chip into a chip level.

10. A method for manufacturing a semiconductor package, comprising the steps of:

providing a plurality of semiconductor chips, each of which is manufactured by the steps comprising;

forming a groove having a side wall on the upper surface of a semiconductor chip having a bonding pad on the upper surface thereof, wherein the groove is closer to the outer perimeter of the semiconductor chip upper surface than the bonding pad;

forming an insulation layer on the side wall of the groove;

forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer;

etching the metal layer to simultaneously form a through silicon via filled with metal in the groove and a distribution layer for connecting the through silicon via and the bonding pad;

removing a portion of the lower surface of the semiconductor chip to reduce the thickness thereof such that a part of the through silicon via at the bottom of the grppve protrudes out of the lower surface of the semiconductor chip; and

stacking two or more of the semiconductor chips so that the through silicon vias from each of the stacked semiconductor chips are connected to each other.

11. The method for manufacturing a semiconductor package according to claim 10, wherein the step of manufacturing each semiconductor chip further comprises the step of:

after removing a portion of the lower surface of the semiconductor chip to reduce the thickness thereof, forming mold parts on the upper and lower surfaces of the semiconductor chip excluding the through silicon via that remains exposed on the upper and lower surfaces of the semiconductor chip formed with mold parts.

12. The method for manufacturing a semiconductor package according to claim 10, wherein the step of forming the metal layer comprises the steps of:

depositing a seed metal layer over the semiconductor chip including the groove;

plating the metal layer over the seed metal layer; and

etching back the metal layer to reduce the thickness thereof.

13. The method for manufacturing a semiconductor package according to claim 10, wherein each of the seed metal layer and the metal layer comprises any one of:

copper (Cu), aluminum (Al), and gold (Au), and an alloy respectively thereof.

14. The method for manufacturing a semiconductor package according to claim 10, wherein the step of simultaneously forming the through silicon via and the distribution layer comprises the steps of:

forming a mask over an area of the metal layer in which the through silicon via and the distribution layer is to be formed;

etching the portion of the metal layer not covered by the mask; and

removing the mask.

15. The method for manufacturing a semiconductor package according to claim 10, wherein the etching of the metal layer is carried out in a wet etching process.

16. The method for manufacturing a semiconductor package according to claim 10, wherein the step of removing the lower surface of the semiconductor chip is carried out in at least one of a grinding process and an etching process.

17. The method for manufacturing a semiconductor package according to claim 10, wherein every step of manufacturing each semiconductor chip as recited in claim 10 is performed to each one of the plurality of semiconductor chips at a wafer level.

18. The method for manufacturing a semiconductor package according to claim 17, further comprising the step of sawing the wafer so as to separate the plurality of semiconductor chips into a chip level.

19. The method for manufacturing a semiconductor package according to claim 10, further comprising the steps of:

attaching the semiconductor chip onto a substrate; and

attaching outside connection terminals to a lower surface of the substrate.

20. The method for manufacturing a semiconductor package according to claim 19, wherein the outside connection terminals are formed as solder balls.