IC WITH MMW TRANSCEIVER COMMUNICATIONS

• US 20080318619A1
• Filed: 08/30/2008
• Published: 12/25/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Markison, Timothy W.
• Granted Patent: US 8,238,275 B2
• Time in Patent Office: Days
• US Class Current: 455/550.1
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: H04M 1/72412 using two-way short-range wireless interfaces
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit (IC) includes a processing module and main memory. The processing module includes a processing core and a first processing module millimeter wave (MMW) transceiver coupled to the processing core. The main memory includes memory and a first memory MMW transceiver coupled to the memory. At least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver.

Claims

1. A circuit comprising:

a processing module including;

a processing core; and

a first processing module millimeter wave (MMW) transceiver coupled to the processing core; and

main memory including;

memory; and

a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver.

2. The circuit of claim 1 further comprises:

the first processing module MMW transceiver including a transmitter section and a receiver section; and

the first memory MWW transceiver section including a transmitter section and a receiver section, wherein the transmitter section of the first processing module MMW transceiver and the receiver section of the first memory MMW transceiver section use a first channel of a plurality of channels for conveying the at least one of an instruction and data from the processing core to the memory and wherein the receiver section of the first processing module MMW transceiver and the transmitter section of the first memory MMW transceiver section use a second channel of the plurality of channels for conveying the at least one of an instruction and data from the memory to the processing core.

3. The circuit of claim 1, wherein the processing module further comprises:

a second processing module MMW transceiver for processing requests from a plurality of peripheral components; and

an arbitration module coupled to the processing core and the second processing module MMW transceiver, wherein the arbitration module arbitrates the execution of the processing requests by the processing core.

4. The circuit of claim 3, wherein each of the plurality of peripheral components comprises:

a peripheral component core; and

a peripheral MMW transceiver, wherein the processing requests and corresponding responses are conveyed between the plurality of peripheral components and the processing core via the second processing module MMW transceiver and the peripheral MMW transceiver using a second channel of a plurality of channels, wherein the conveying of the data between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver uses a first channel of the plurality of channels.

5. The circuit of claim 3, wherein the arbitration module functions to arbitrates the execution of the processing requests by at least one of:

coordinating a time division multiple access of the second channel among the plurality of peripheral components;

coordinating access of the plurality of peripheral devices to the second channel using an orthogonal frequency division multiplexing channel usage scheme;

transmitting access queries to the plurality of peripheral components and arbitrating based on corresponding responses;

coordinating a carrier sense multiple access with collision avoidance protocol; and

coordinating a hierarchy scheme among the plurality of peripheral components to access the second channel.

6. The circuit of claim 1, wherein the main memory further comprises:

a second memory MMW transceiver for processing memory requests from a plurality of peripheral components.

7. The circuit of claim 6, wherein each of the plurality of peripheral components comprises:

a peripheral component core; and

a peripheral MMW transceiver, wherein the memory requests and corresponding responses are conveyed between the plurality of peripheral components and the memory via the second memory MMW transceiver and the peripheral MMW transceiver using a second channel of a plurality of channels, wherein the conveying of the data between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver uses a first channel of the plurality of channels.

8. The circuit of claim 1 further comprises:

a graphics interface module including;

a graphics interface core; and

a graphics MMW transceiver;

wherein the main memory further includes;

a second memory MMW transceiver, wherein graphics data is conveyed between the graphics interface core and main memory via the second MMW transceiver and the graphics MMW transceiver using a second channel of a plurality of channels, wherein the conveying of the data between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver uses a first channel of the plurality of channels.

9. A circuit comprises:

a processing module including;

a processing core;

a first processing module millimeter wave (MMW) transceiver coupled to the processing core; and

a second processing module MMW transceiver coupled to the processing core;

main memory including;

memory;

a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver using a first channel of a plurality of channels; and

a second memory MMW transceiver coupled to the memory; and

an access module including;

an access control module;

a first access control module MMW transceiver coupled to the access control module; and

a second access control module MMW transceiver coupled to the access control module, wherein a memory access request or a processing request is received via the first access control module MMW transceiver using a second channel of the plurality of channels, wherein the access module conveys the processing request to the processing core via the second access control module MMW transceiver and the second processing module MMW transceiver, and wherein the access module conveys the memory access request to the memory via the second access control module MMW transceiver and the second memory MMW transceiver.

10. The circuit of claim 9 further comprises:

the first processing module MMW transceiver including a transmitter section and a receiver section; and

the first memory MWW transceiver section including a transmitter section and a receiver section, wherein the transmitter section of the first processing module MMW transceiver and the receiver section of the first memory MMW transceiver section use the first channel for conveying the at least one of an instruction and data from the processing core to the memory and wherein the receiver section of the first processing module MMW transceiver and the transmitter section of the first memory MMW transceiver section use a fourth channel of the plurality of channels for conveying the at least one of an instruction and data from the memory to the processing core.

12. The circuit of claim 9 further comprises:

a graphics interface module including;

a graphics interface core; and

a graphics MMW transceiver;

wherein the main memory further includes;

a third memory MMW transceiver, wherein graphics data is conveyed between the graphics interface core and main memory via the third MMW transceiver and the graphics MMW transceiver using a fourth channel of the plurality of channels.

13. The circuit of claim 9, wherein the access control module functions to:

convey the processing request to the processing core via the second access control module MMW transceiver and the second processing module MMW transceiver using a third channel of the plurality of channels; and

convey the memory access request to memory via the second access control module MMW transceiver and the second memory MMW transceiver using the third channel.

14. The circuit of claim 9, wherein the second access control module MMW transceiver comprises:

a memory MMW transceiver that conveys the memory access request to the second memory MMW transceiver using a third channel of the plurality of channels; and

a processing module transceiver that conveys the processing request the second processing module MMW transceiver using a fourth channel of the plurality of channels.

11. The circuit of claim further comprises:

a plurality of peripheral components, wherein each of the plurality of peripheral components includes;

a peripheral component core; and

a peripheral MMW transceiver, wherein the memory access request or the processing request and a corresponding response are conveyed between the peripheral component core and the access control module via the second access control module MMW transceiver and the peripheral MMW transceiver using the second channel.

15. A circuit comprises:

a core access control module including;

a first core millimeter wave (MMW) transceiver operable to convey a memory message with main memory; and

a second core MMW transceiver operable to convey a processing message with a processing module; and

a peripheral access control module coupled to the core access control module, wherein the peripheral access control module includes;

a peripheral access MMW transceiver operable to convey a peripheral message with one of a plurality of peripheral components.

16. The circuit of claim 15 further comprises:

the core access control module including a third core MMW transceiver; and

the peripheral access control module including a second peripheral MMW transceiver, wherein the third core MMW transceiver and the second peripheral MMW transceiver provide the coupling between the core access control module and the peripheral access control module.

17. The circuit of claim 15 further comprises:

the processing module including;

a processing core; and

a first processing module MMW transceiver coupled to the processing core;

wherein the second core MMW transceiver conveys the processing message with the first processing module MMW transceiver.

18. The circuit of claim 15 further comprises:

the main memory including;

memory; and

a first memory MMW transceiver coupled to the memory, wherein the first core MMW transceiver conveys the memory message with the first memory MMW transceiver.

19. The circuit of claim 15 further comprises:

the plurality of peripheral components, wherein each of the peripheral components includes;

a peripheral core; and

a peripheral MMW transceiver coupled to the peripheral core, wherein the peripheral MMW transceiver conveys the peripheral message with the peripheral access MMW transceiver.

20. The circuit of claim 15, wherein the core access control module further comprises:

a control module operable to coordinate the conveying of the memory message with main memory and the conveying of the processing message with the processing module.

21. The circuit of claim 15, wherein the peripheral access control module further comprises:

a control module operable to coordinate conveying a plurality of peripheral message with the plurality of peripheral components.