METHOD AND SYSTEM FOR CREATING ARRAY DEFECT PARETOS USING ELECTRICAL OVERLAY OF BITFAIL MAPS, PHOTO LIMITED YIELD, YIELD, AND AUTO PATTERN RECOGNITION CODE DATA

• US 20080319568A1
• Filed: 06/22/2007
• Published: 12/25/2008
• Est. Priority Date: 06/22/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Winslow, Jonathan K. II, Berndlmaier, Zachary E.
• Application Number:
  US11/766,844
• Publication Number:
  US 20080319568A1
• Time in Patent Office: Days
• US Class Current: 700/110
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 5/50 using two or more images, e.g. averaging or subtraction
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525

Abstract

A method for creating defect array paretos for semiconductor manufacturing, the method includes: merging a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures; merging the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios; wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.

Claims

1. A method for creating defect array paretos for semiconductor manufacturing, the method comprising:

merging a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures;

merging the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios;

wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and

wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.

2. The method of claim 1, wherein the calculation of kill ratios facilitates the statistical calculation of the probability of failure for a given APRC code.

3. The method of claim 1, wherein the merging of the paretos of APRC codes for array failures that are not repairable with the set of ETPLY creates a weighted defect pareto for unfixable array failures;

and

wherein the weighted defect pareto for unfixable array failures provides a quantification of array yield loss associated with each physical defect mechanism observed during PLY.

4. The method of claim 1, wherein the merging of the paretos of APRC codes for semiconductor devices that are repairable at wafer final test with the set of ETPLY creates a weighted defect pareto for fixable array failures;

and

wherein the weighted defect pareto for fixable array failures provides a quantification of physical defect mechanisms observed during PLY that caused array failures, but were fixable via a redundancy in the array.

5. A system for creating defect array paretos for semiconductor manufacturing, the system comprising:

a set of hardware and networking resources;

an algorithm implemented on the set of hardware and networking resources;

wherein the algorithm merges a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures;

wherein the algorithm merges the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios;

wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and

wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.

6. The system of claim 5, wherein the calculation of kill ratios facilitates the statistical calculation of the probability of failure for a given APRC code.

7. The system of claim 5, wherein the merging of the paretos of APRC codes for array failures that are not repairable with the set of ETPLY creates a weighted defect pareto for unfixable array failures;

and

wherein the weighted defect pareto for unfixable array failures provides a quantification of array yield loss associated with each physical defect mechanism observed during PLY.

8. The system of claim 5, wherein the merging of the paretos of APRC codes for semiconductor devices that are repairable at wafer final test with the set of ETPLY creates a weighted defect pareto for fixable array failures;

and

wherein the weighted defect pareto for fixable array failures provides a quantification of physical defect mechanisms observed during PLY that caused array failures, but were fixable via a redundancy in the array.