MONITORED NOTIFICATION FACILITY FOR REDUCING INTER-PROCESS / INTER-PARTITION INTERRUPTS

• US 20080320194A1
• Filed: 06/20/2007
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Chin, Yau Ning, Sheu, John Te-Jui, Vega, Rene
• Granted Patent: US 7,913,009 B2
• Time in Patent Office: Days
• US Class Current: 710/263
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.

Claims

1. A method of handling an asynchronous message sent over a channel comprising:

writing a message to a memory location shared between a sender and a receiver; and

requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory.

2. The method of claim 1, further comprising:

polling the trigger memory for the pending interrupt before the specified latency has elapsed;

canceling the pending interrupt; and

processing at least one message in the shared memory.

3. The method of claim 1, further comprising:

polling the trigger memory for the pending interrupt when accessing the memory location shared between the sender and the receiver.

4. The method of claim 2, wherein requesting that an interrupt be transmitted includes writing a setting value to trigger memory, and canceling the pending interrupt includes writing a canceling value to the trigger memory.

5. The method of claim 1, comprising:

utilizing at least one of an message initiation, message completion, a hardware interrupt, and an explicit poll by a process to poll the trigger memory.

6. The method of claim 1, comprising:

utilizing the sending of a message in response to at least one of a confirmation message, and completion message to poll the trigger memory.

7. The method of claim 1, further comprising:

writing at least one more additional message into the shared memory location before the specified latency has elapsed, wherein an interrupt for the one or more additional messages is not requested.

8. The method of claim 1, further comprising:

determining a rate at which at least one of an input/output device, the sender, and the receiver handles one or more messages; and

utilizing the rate when requesting the specified latency.

9. A method of sending an interrupt deferred for a specified latency comprising:

registering a trigger memory with a privileged process, and polling the trigger memory to determine if a sender has set a trigger associated with a specified latency, and sending an interrupt to an associated receiver when the trigger is set, and the specified latency has elapsed.

10. The method of claim 9, wherein the trigger memory is polled during at least one control switch to a privileged process.

11. The method of claim 9, further comprising:

determining a time interval between control switches;

determining that the time interval between control switches is less than the specified latency associated with the trigger; and

omitting the polling of the trigger during at least one control switch.

12. The method of claim 9, further comprising:

determining a time interval between control switches;

determining that the time interval between control switches is greater than the specified latency of at least one trigger; and

forcing at least one additional control switch, and polling the trigger during the at least one forced control switch.

13. The method of claim 9, further comprising:

dividing a plurality of triggers into a plurality of trigger sets, assigning each trigger set to one of a plurality of processors; and

instructing a specific processor of the plurality processors to check at least one trigger in a trigger set that the specific processor was not assigned.

14. The method of claim 13, further comprising:

polling the plurality of trigger sets; and

sending any pending interrupts in the plurality of triggers before a processor associated with monitoring the plurality the trigger sets enters an idle state.

15. The method of claim 9, further comprising:

identifying that a trigger has been set and recording the time that the at least one trigger was identified; and

calculating whether the specified latency has elapsed based on a current time and the recorded time.

16. The method of claim 9, wherein the trigger includes information indicating a time the trigger was set.

17. The method of claim 9, wherein a trigger with a specified latency can be manipulated without initiating a control switch to a privileged process.

18. A method of sending a deferred interrupt to a process comprising:

registering a trigger memory, the trigger memory configured to allow a sender to set a trigger indicating that an interrupt is needed after a specified latency; and

determining a rate of interrupts sent to an associated receiver of a shared memory location, and un-registering the trigger memory location if the rate of interrupts is lower than a predetermined threshold, otherwise polling the trigger memory to check if the trigger was set, and sending an interrupt to the associated receiver when the trigger is set and the specified latency has elapsed.

19. The method of claim 18, wherein the rate of interrupts is determined based at least one of a requested specified latency, a number of registered triggers, and a performance calculation, wherein the performance calculation includes balancing the performance costs of polling the trigger against the performance costs of calling a privileged process to send an interrupt.

20. The method of claim 18, further comprising:

receiving a request to send an interrupt to an associated receiver, wherein the trigger memory is un-registered; and

registering the trigger memory when the rate of interrupts exceeds the predetermined threshold.