Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices

• US 20080320214A1
• Filed: 08/05/2008
• Published: 12/25/2008
• Est. Priority Date: 12/02/2003
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Chow, David Q., Yu, Frank
• Granted Patent: US 8,341,332 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells

Abstract

A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

Claims

1. A multi-level-control multi-flash device comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned single-chip flash-memory device to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a plurality of single-chip flash-memory devices that include the assigned single-chip flash-memory device, wherein a single-chip flash-memory device comprises;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;

a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); and

non-volatile memory blocks, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller;

whereby address mapping is performed at two levels to access the non-volatile memory blocks.

2. The multi-level-control multi-flash device of claim 1 wherein the smart storage switch further comprises:

a parity generator for generating error detecting code for the host data, the error correcting code being stored with the host data,

whereby error detection code is added at a top level by the smart storage switch.

3. The multi-level-control multi-flash device of claim 1 further comprising:

a local clock source, within each of the plurality of single-chip flash-memory devices, for generating local clocks for clocking the NVM controllers and interfaces to the non-volatile memory blocks,

wherein local clocks are generated within each of the plurality of single-chip flash-memory devices.

4. The multi-level-control multi-flash device of claim 1 further comprising:

a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;

wherein the non-volatile memory blocks in the plurality of single-chip flash-memory device are non-volatile memory that retain data when power is disconnected;

wherein the smart storage switch further comprises;

a virtual buffer bridge, coupled between the smart storage transaction manager and the volatile memory buffer.

5. The multi-level-control multi-flash device of claim 1 wherein the smart storage transaction manager further comprises:

a data striping unit that divides the host data into data segments that are assigned to different ones of the plurality of single-chip flash-memory devices,

whereby the host data is striped at the top level.

6. The multi-level-control multi-flash device of claim 1 wherein the smart storage switch further comprises:

mode logic, coupled to the smart storage transaction manager, for determining when to set the smart storage transaction manager in a hub mode and when to set the smart storage transaction manager in a switch mode;

wherein the smart storage transaction manager responds to the host as a single-endpoint when the mode logic indicates the switch mode, wherein the smart storage transaction manager reports to the host a total aggregate memory capacity of all non-volatile memory blocks in all single-chip flash-memory devices in the plurality of single-chip flash-memory devices,

wherein the smart storage switch causes the host to see the plurality of single-chip flash-memory devices as a single virtual flash-memory device when the mode logic indicates the switch mode.

7. The multi-level-control multi-flash device of claim 1 wherein the single-chip flash memory device comprises a flash module that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

8. The multi-level-control multi-flash device of claim 1 wherein the smart storage transaction manager further comprises:

a reordering unit that re-orders a sequence of transactions from the host into an altered order of operations sent to the plurality of single-chip flash-memory devices through the virtual storage bridge,

whereby host transactions are re-ordered at a top level.

9. A storage device comprising:

an upstream interface to a host that generates host data and host commands in a host sequence of commands;

a single-chip flash-memory device having a plurality of flash memory blocks for storing the host data in non-volatile solid-state memory that retains data when power is disconnected;

a virtual storage processor that assigns host commands to the single-chip flash-memory device, the virtual storage processor also storing attributes obtained from the single-chip flash-memory device, the attributes including memory capacities, wherein the virtual storage processor reports an aggregate sum of the memory capacities to the host;

a lower-level controller in the single-chip flash-memory device, the lower-level controller comprising;

a remapping unit for converting logical addresses received from the upstream interface into physical addresses for accessing the plurality of flash memory blocks in the single-chip flash-memory device;

a wear-leveling unit for assigning new host data to a less-worn block in the plurality of flash memory blocks within the single-chip flash-memory device; and

a bad block unit for tracking defective memory blocks within the single-chip flash-memory device, the bad block unit preventing the new host data from being stored in a defective memory block being tracked.

10. The storage device of claim 9 wherein the single-chip flash memory device comprises a flash module that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

11. A smart-switched multiple non-volatile-memory system comprising:

an upstream interface to a host that generates host data and host commands in a host sequence of commands;

a smart storage transaction manager, coupled to the upstream interface, for re-ordering the host commands from the host sequence into a reordered sequence of operations;

a plurality of single-chip flash-memory devices each having a plurality of flash memory blocks for storing the host data in non-volatile solid-state memory that retains data when power is disconnected;

a virtual storage processor that assigns host commands to an assigned device in the plurality of single-chip flash-memory devices, the virtual storage processor also storing attributes obtained from each of the plurality of single-chip flash-memory devices, the attributes including memory capacities, wherein the virtual storage processor reports an aggregate sum of the memory capacities to the host;

a virtual storage bridge, coupled between the smart storage transaction manager and the plurality of single-chip flash-memory devices;

a lower-level controller in each of the plurality of single-chip flash-memory devices, the lower-level controller in a single-chip flash-memory device comprising;

a remapping unit for converting logical addresses received from the virtual storage bridge into physical addresses for accessing the plurality of flash memory blocks in the single-chip flash-memory device;

a wear-leveling unit for assigning new host data to a less-worn block in the plurality of flash memory blocks within the single-chip flash-memory device; and

a bad block unit for tracking defective memory blocks within the single-chip flash-memory device, the bad block unit preventing the new host data from being stored in a defective memory block being tracked;

whereby the virtual storage processor aggregates memory capacities of the plurality of single-chip flash-memory devices which each re-map and wear-level flash memory blocks within a single-chip flash-memory device.

12. The smart-switched multiple non-volatile-memory system of claim 11 wherein the smart storage transaction manager further comprises:

a wear monitor for monitoring wear levels reported by the plurality of single-chip flash-memory devices;

a storage volume installer, activated by the wear monitor when a single-chip flash-memory device reports a high wear level above a threshold, for replacing the single-chip flash-memory device with high wear level with a replacement single-chip flash-memory device,

whereby wear leveling is performed at a lower level by each of the plurality of single-chip flash-memory devices and storage volume replacement is performed by the smart storage transaction manager.

13. The smart-switched multiple non-volatile-memory system of claim 11 wherein the smart storage transaction manager further comprises:

a data striping unit for segmenting host data into data segments stored on several of the plurality of single-chip flash-memory devices;

,

wherein each single-chip flash-memory device further comprises an error-correction code (ECC) unit for appending ECC to the host data sent to the assigned device in the plurality of single-chip flash-memory device for storage in the plurality of flash memory blocks,

whereby high-level data striping is performed before the host data is sent to the plurality of single-chip flash-memory devices.

14. The smart-switched multiple non-volatile-memory system of claim 13 further comprising:

a dynamic-random-access memory (DRAM) buffer for temporarily storing the host data;

a virtual buffer bridge between the DRAM buffer and the smart storage transaction manager,

whereby host data is buffered by the DRAM buffer.

15. The smart-switched multiple non-volatile-memory system of claim 11 wherein the smart storage transaction manager further comprises:

an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of single-chip flash-memory devices,

whereby the plurality of single-chip flash-memory devices are accessed in interleaves.

16. The smart-switched multiple non-volatile-memory system of claim 13 wherein the single-chip flash-memory devices comprises a flash module that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

17. A data-striped solid-state-disk comprising:

volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected;

smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising;

upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address;

smart storage transaction manager means for managing transactions from the host;

virtual storage processor means for translating the host address to an assigned single-chip flash-memory device to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping;

virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus;

virtual buffer bridge means, coupled between the smart storage transaction manager means and the volatile memory buffer means;

reordering means for re-ordering a sequence of transactions from the host into an altered order of operations sent through the virtual storage bridge means;

data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of single-chip flash-memory devices;

a plurality of single-chip flash-memory devices that include the assigned single-chip flash-memory device, wherein a single-chip flash-memory device comprises;

lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means;

second-level map means, in the lower-level controller means, for mapping the LBA to a physical block address (PBA); and

non-volatile memory blocks, coupled to the lower-level controller means, for storing the host data at a block location identified by the PBA generated by the second-level map means in the lower-level controller means;

wherein the non-volatile memory blocks in the plurality of single-chip flash-memory device are non-volatile memory that retain data when power is disconnected,

whereby address mapping is performed at two levels to access the non-volatile memory blocks.

18. The data-striped solid-state-disk of claim 17 wherein the lower-level controller means further comprises:

wear-leveler means for assigning host data to a less-worn block in the non-volatile memory blocks, the less-worn block having a lower wear count value than other blocks, wherein the wear-leveler means examines wear count values to assign host data to blocks;

bad block manager means, having a list of faulty blocks in the non-volatile memory blocks, for causing the wear-leveler means to avoid assigning host data to a block in the list of faulty blocks,

whereby wear-leveling and bad block management are performed at a lower level within each of the plurality of single-chip flash-memory devices.

19. The data-striped solid-state-disk of claim 18 wherein the non-volatile memory blocks comprise two flash die that are stacked together and accessible by interleaving, and wherein each of the two flash die comprises two planes that are accessible by interleaving;

wherein a size of the data segment is equal to four pages per channel, and each channel has one of the plurality of single-chip flash-memory devices, whereby the host data is striped with a depth to match the plurality of single-chip flash-memory devices.

20. The data-striped solid-state-disk of claim 17 wherein a stripe depth is equal to N times a stripe size, wherein N is a whole number of the plurality of single-chip flash-memory devices, and wherein the stripe size is equal to a number of pages that can be simultaneously written into one of the plurality of single-chip flash-memory devices.

21. The data-striped solid-state-disk of claim 17 wherein the single-chip flash-memory device comprises a flash module that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.