MEMORY-SHARING SYSTEM DEVICE

• US 20080320243A1
• Filed: 06/20/2008
• Published: 12/25/2008
• Est. Priority Date: 06/22/2007
• Status: Abandoned Application

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Kamata, Eiichi, MITSUZUKA, Hirofumi
• Application Number:
  US12/143,374
• Publication Number:
  US 20080320243A1
• Time in Patent Office: Days
• US Class Current: 711/153
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

A memory-sharing system device has a shared memory, divided into forward-direction and backward-direction memory areas; a first processor inputting transfer data in the forward direction, writing the data to the forward-direction memory area, reading transfer data in the backward direction from the backward-direction memory area and outputting the data; and a second processor for transferring data in the back-ward direction. The first or second processor sets memory release criteria for the forward-direction and backward-direction memory areas respectively, and, when the used memory area reaches the memory release criterion, performs memory release processing. The first or second processor monitors the forward-direction and the backward-direction data transfer speed, changes the memory release criterion depending on the data transfer speed.

Claims

1. A memory-sharing system device which shares common memory, comprising:

a shared memory, divided into a forward-direction memory area and a backward-direction memory area;

a first processor, which input data for transfer in a forward direction from a lower-layer side and writes the data to the forward-direction memory area, and reads data for transfer in a backward direction from the backward-direction memory area and outputs the data to the lower-layer side; and

a second processor, which input data for transfer in the backward direction from an upper-layer side and writes the data to the backward-direction memory area, and reads data for transfer in the forward direction from the forward-direction memory area and outputs the data to the upper-layer side, wherein

the first or second processor sets memory release criteria for the forward-direction memory area and for the backward-direction memory area respectively, and, when the used memory area for which the transfer data reading has been completed reaches the memory release criteria, performs memory release processing to release the used memory area for enabling writing; and

the first or second processor monitors a forward-direction data transfer speed and a backward-direction data transfer speed, sets the memory release criterion for the forward-direction memory area or for the backward-direction memory area to a first memory release criterion when the corresponding transfer speed is a first transfer speed, and sets the memory release criterion to a second memory release criterion smaller than the first memory release criterion when the corresponding transfer speed is a second transfer speed higher than the first transfer speed.

2. The memory-sharing system device according to claim 1, wherein

the memory release criteria comprises a read criterion corresponding to the area in which reading is completed and a write criterion corresponding to the area in which writing is completed, and

the first or second processor performs the memory release processing when the used memory area reaches the read criterion and the memory area in which writing is completed reaches the write criterion.

3. The memory-sharing system device according to claim 1, wherein

the first and second processors perform, in units of memory block areas having prescribed size, transfer data writing and reading;

when the first or second processors writes transfer data to a corresponding memory area, the first or second processor supplies the write address as well as a write interrupt notification to the second or first processor;

upon receiving the write interrupt notification, the second or first processor stores the write address in read queue matrix memory, and thereafter, when reading the transfer data at the write address stored in the read queue matrix memory, if the used memory area has reached the memory release criterion, issues a release interrupt notification to the first or second processor; and

upon receiving the release interrupt notification, the first or second processor performs the release processing for the used memory area.

4. The memory-sharing system device according to claim 3, wherein the first and second processors manage release pointers respectively indicating addresses of released memory areas in the forward-direction and backward-direction memory areas, and update the release pointers according to the used memory areas in the release processing.

5. The memory-sharing system device according to claim 4, wherein the first and second processors determine sizes of the memory areas in which writing is completed from the release pointers and the latest write address in the forward-direction and backward-direction memory areas, and determine sizes of the used memory areas in which reading is completed from the release pointers and the write addresses at the time of reading.

6. The memory-sharing system device according to claim 1, wherein

the first processor monitors the transmission speed of data transferred in the forward direction and variably controls the memory release criterion of the forward-direction memory area according to the monitored transmission speed, and

the second processor monitors the transmission speed of data transferred in the backward direction and variably controls the memory release criterion of the backward-direction memory area according to the monitored transmission speed.

11. A communication terminal device, comprising:

the memory-sharing system device according to any of claims 1 through 10;

a communication device, which outputs data for transfer in the forward direction to the first processor and takes input of data for transfer in the backward direction from the first processor; and

an application device, which takes input of data for transfer in the forward direction from the second processor, and outputs data for transfer in the backward direction to the second processor.

7. A memory-sharing system device which shares common memory, comprising:

a shared memory, divided into a forward-direction memory area and a backward-direction memory area;

a first processor, which input data for transfer in a forward direction from a lower-layer side and writes the data to the forward-direction memory area, and reads data for transfer in a backward direction from the backward-direction memory area and outputs the data to the lower-layer side; and

a second processor, which input data for transfer in the backward direction from an upper-layer side and writes the data to the backward-direction memory area, and reads data for transfer in the forward direction from the forward-direction memory area and outputs the data to the upper-layer side, wherein

the first or second processor monitors a forward-direction data transfer speed and a backward-direction data transfer speed, and modifies a size ratio of the forward-direction memory area and backward-direction memory area, according to both of the transfer speeds, such that the size of the memory area corresponding to the higher transfer speed is greater.

8. The memory-sharing system device according to claim 7, wherein

the first or second processor sets memory release criteria for the forward-direction memory area and backward-direction memory area respectively, and when the used memory area in which reading of the transfer data has been completed reaches the memory release criterion, performs memory release processing to release the used memory area for enabling writing;

and

the first or second processor sets the memory release criteria for the forward-direction memory area and backward-direction memory area to a first memory release criterion when the corresponding transfer speed is a first transfer speed, and to a second memory release criterion which is smaller than the first memory release criterion when the corresponding transfer speed is a second transfer speed which is greater than the first transfer speed.

9. The memory-sharing system device according to claim 8, wherein the first or second processor sets the memory release criteria for the forward-direction memory area and backward-direction memory area to a third memory release criterion when the memory area is of a first size and to a fourth memory release criterion, which is larger than the third memory release criterion, when the memory area is of a second size larger than the first size.

10. The memory-sharing system device according to claim 8, wherein

the memory release criteria includes a read criterion corresponding to the area in which reading is completed and a write criterion corresponding to the area in which writing is completed, and

the first or second processor performs the memory release processing when the used memory area reaches the read criterion and the memory area in which writing is completed reaches the write criterion.