VARIOUS METHODS AND APPARATUS FOR CONFIGURABLE MAPPING OF ADDRESS REGIONS ONTO ONE OR MORE AGGREGATE TARGETS

• US 20080320255A1
• Filed: 06/24/2008
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Abandoned Application

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Wingard, Drew E., Swarbrick, Ian Andrew, Chou, Chien-Chun, Vakilotojar, Vida, Hamilton, Stephen W.
• Application Number:
  US12/145,257
• Publication Number:
  US 20080320255A1
• Time in Patent Office: Days
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Claims

1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements an address map with assigned address for target IP cores in the integrated circuit to route the transactions between the target IP cores and initiator IP cores in the integrated circuit and a first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map, where each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels, wherein the address map is divided up into two or more regions, each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

2. The apparatus of claim 1, wherein a first memory channel has a first memory interleave segment of a first size controlled by a configurable parameter of a first region in the address map and a second interleave segment of a second size controlled by a configurable parameter of a second region in the address map.

3. The apparatus of claim 1, wherein each memory interleave segment of those memory channels being defined and interleaved in the address space at a defined length bounded by a minimum burst size configured into one or more DRAM devices that form the memory channel and an anticipated maximum DRAM memory page size for the supported configurations of the memory channel, and the transactions include one or more requests and one or more optional responses.

4. The apparatus of claim 1, wherein the configurable parameter to control the defined length of the memory interleave segments in the address space assigned to a given region is based on an anticipated type of application expected to have transactions with the memory interleave segments in that region.

5. The apparatus of claim 1, wherein the configuration parameters in each region may be configured at the time selected from the group consisting of when the hardware is built, programmed in by OS software at run time, programmed in through electronic design software at design time, physically changed when the device is fabricated by selecting different on-chip pin combinations, changeable after simulations have been run via software, dynamically changed by asserting/de-asserting voltage is carried on particular control lines routed throughout the chip and any combination thereof.

6. The apparatus of claim 1, wherein a first region in the address map has defined memory interleave segments allocated to that region from a first memory channel that have a configured granularity at a first amount of bytes and a second region in the address map has defined memory interleave segments allocated to that region from the first memory channel that have a configured granularity at a second amount of bytes.

7. The apparatus of claim 1, wherein each region in the address map may set its own configurable parameter to control the defined length of the memory interleave segments in the address space assigned to that region based on 1) anticipated programs using memory in that region and 2) to take advantage of a principle of locality of a type of anticipated program using the memory in that region.

8. The apparatus of claim 1, wherein the configurable configuration parameters flexibly support a multiple channel configuration that is dynamically changeable and enable a single already-designed System-on-a-Chip design to support a wide range of packaging options that use different external memory configurations and to re-configure channel-to-region assignments and interleaving boundaries between channels to better support different modes of operation of a single package.

9. The apparatus of claim 1, wherein the configuring of the configuration parameters may be supplied by a designer via number of ways selected from the group consisting of software writing to a register, selecting on-chip pins to set a selectable pin configuration that establishes a configuration mode with logic tied to the selectable pin configuration, activating dedicated control lines carrying this configuration information so components can reference the configuration parameters on these control lines routed throughout the chip, embedding into read-only memories that are interrogatable by software, mating connections to proper package solder bonds, and any combination thereof.

10. The apparatus of claim 1, wherein a user may supply configuration parameters for variables selected from the group consisting of 1) list a number of discreet IP memory cores, 2) list a number of regions in an address map, 3) mapping discreet IP memory cores to regions in the address map 4) remove a channel from a region, which then may collapse the system address populated by a remaining channel in that region;

5) reset a channel'"'"'s presence in a region;

     6) alter a system usable space in one or more memory channels in an aggregate target such as even smaller in size/narrower,

     7) alter a defined size granularity of memory interleave segments;

     8) determine the number of channels in one region, and reassign channels from one region to another, which all will reset an interleaving boundary, have some regions with channels and other regions with no channels and

     9) any combination thereof.

11. The apparatus of claim 1, wherein configuration logic cooperating with the received configuration parameters limits an amount of legal configurations with the memory system from general purpose to several application specific purposes to limit an amount of configurable parameters that must be communicated and to limit an amount of logic and hardware physically present on chip to make the memory general purpose for all applications.

12. The apparatus of claim 1, further comprising:

a table maintained locally in each agent receives the region'"'"'s configuration parameter values from a central source of configuration parameters to allow flexible re-configuration of a multiple channel aggregate target.

13. The apparatus of claim 1, further comprising:

a single central configuration register from a user interface perspective exists for a designer to program configuration parameters into this register and the register fields of the central configuration register are configured as export constants.

14. A machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the apparatus of claim 1.

15. The apparatus of claim 14, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representations of the apparatus.

16. The apparatus of claim 1, wherein a number of channels in an address region is configurable at run time and a first address region and a second address region both map to contain a first channel.

17. A method, comprising:

configurable mapping of address regions onto one or more aggregate target IP cores in a group of target IP cores, wherein a first aggregate target includes two or more channels that are interleaved in an address space for the first aggregate target in an address map, where each channel is divided up in defined interleave segments and then interleaved with interleave segments from other channels, where transactions will be routed over an interconnect between the target IP cores and one or more initiator IP cores according to an address map with assigned address for the target IP cores, wherein the address map is divided up into two or more address regions;

configuring parameters associated with the address regions and the interleave segments, wherein the configuration parameters in each address region is configurable; and

configuring a first interleave segment to a first size controlled by a configurable parameter of a first address region in the address map and configuring a second interleave segment to a second size controlled by a configurable parameter of a second address region in the address map, wherein each interleave segment of those channels being defined and interleaved in the address space of the regions at a size granularity chosen by a designer and independent of the size granularity of memory interleave segment selected in the other address region.

18. The method of claim 17, wherein the configuration parameters in each address region is configurable at the time selected from the group consisting of when the hardware is built, programmed in by Operating System driver software at run time, programmed in through electronic design software at design time, physically changed when the device is fabricated or tested by selecting different on-chip pin combinations, changed after simulations have been run via software, dynamically changed by setting voltage levels on external signal pins and any combination thereof, and the channels are memory channels with memory interleave segments.

19. The method of claim 18, wherein a user may supply configuration parameters for variables selected from the group consisting of 1) list a number of discreet IP memory cores, 2) list a number of regions in an address map, 3) mapping discreet IP memory cores to regions in the address map 4) remove a channel from a region, which then may collapse the system address populated by a remaining channel in that region;

5) reset a channel'"'"'s presence in a region;

     6) alter a system usable space in one or more memory channels in an aggregate target such as even smaller in size/narrower,

     7) alter a defined size granularity of memory interleave segments;

     8) determine the number of channels in one region, and reassign channels from one region to another, which all will reset an interleaving boundary, have some regions with channels and other regions with no channels and

     9) any combination thereof.

20. An Integrated Circuit, comprising:

one or more initiator IP cores;

multiple target IP cores including memory IP cores; and

an interconnect to communicate transactions between the one or more initiator IP cores and the multiple target IP cores coupled to the interconnect, wherein the interconnect implements an address map with assigned address for target IP cores in the integrated circuit to route the requests between the target IP cores and initiator IP cores in the integrated circuit and a first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map, where each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels, wherein the address map may be divided up into two or more regions, each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable, and a first region in the address map has defined memory interleave segments allocated to that region from a first memory channel that have a configured size granularity at a first amount of bytes and a second region in the address map has defined memory interleave segments allocated to that region from the first memory channel that have a configured granularity at a second amount of bytes.