MICROPROGRAMMED PROCESSOR HAVING MUTIPLE PROCESSOR CORES USING TIME-SHARED ACCESS TO A MICROPROGRAM CONTROL STORE

• US 20080320280A1
• Filed: 06/20/2008
• Published: 12/25/2008
• Est. Priority Date: 06/21/2007
• Status: Active Grant

• Current Assignee: Imsys AB (Samsung Electronics Co. Ltd.)
• Original Assignee: Imsys Technologies AB (Samsung Electronics Co. Ltd.)
• Inventors: Blixt, Stefan
• Granted Patent: US 8,060,727 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically comprises at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable means (30) for providing time-shared access to the microprogram control store by the processor cores.

Claims

1. A microprogrammed processor comprising:

at least two processor cores;

a common internal microprogram control store including microcode instructions for controlling at least the internal standard operation of said at least two processor Cores;

means for providing time-shared access to said microprogram control store by said at least two processor cores.

2. The microprogrammed processor of claim 1, wherein the processor cores are configured for executing microcode instructions independently of each other.

3. The microprogrammed processor of claim 2, wherein each processor core is configured to first read a microcode instruction from the microprogram control store and then execute the microcode instruction, and while one of said processor cores executes a microcode instruction, another one of said processor core accesses the microprogram control store and reads another microcode instruction.

4. The microprogrammed processor of claim 2, wherein separate processor cores are configured for executing completely different microprogram tasks independently of each other.

5. The microprogrammed processor of claim 1, wherein each of said at least two processor cores has at least one internal execution unit, with control logic, for executing microcode instructions from said common microprogram control store, and the execution units of said at least two processor cores share said common microprogram control store.

6. The microprogrammed processor of claim 5, wherein the execution units of said at least two processor cores and said common microprogram control store are provided on the same integrated circuit (IC) chip, effectively providing a microprogrammed multi-core microprocessor using a common microprogram control store.

7. The microprogrammed processor of claim 5, wherein each of said at least two processor cores also has an associated microinstruction register for storing a microcode instruction from said microprogram control store available for execution by a corresponding execution unit.

8. The microprogrammed processor of claim 5, wherein the execution units of said at least two processor cores share portions of a microprogram in said common microprogram control store, while further being used for executing different microprogram tasks independently of each other.

9. The microprogrammed processor of claim 1, wherein said means for providing time-shared access comprises means for generating clock signals for said at least two cores such that the microinstruction cycles of the processor cores are executed out of phase.

10. The microprogrammed processor of claim 9, wherein said processor cores includes two processor cores and each of the cores starts its microinstruction cycle when the other of the two cores is halfway through its cycle.

11. The microprogrammed processor of claim 1, wherein said microprogrammed processor is a microcode-controlled processor.

12. The microprogrammed processor of claim 11, wherein said microprogram control store includes microcode instructions for fetching and executing machine instructions.

13. A computer system comprising a microprogrammed processor of claim 1.

14. A method of operating a microprogrammed processor having at least two processor cores, said method comprising the steps of:

providing a common microprogram control store including microcode instructions for controlling at least the internal standard operation of said at least two processor cores; and

providing access to said common microprogram control store by said at least two processor cores on time-shared basis.

15. The method of claim 14, wherein said, step of providing access comprises the step of generating clock signals for said at least two processor cores such that the microinstruction cycles of the processor cores are executed out of phase.