PROCESSING MODULE WITH MMW TRANSCEIVER INTERCONNECTION

• US 20080320281A1
• Filed: 08/30/2008
• Published: 12/25/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Markison, Timothy W.
• Granted Patent: US 8,438,322 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A processing module includes a fetch and decode module, an instruction register, a data register, an execution module, and a MMW transceiver section. The fetch and decode module is operable to fetch and decode an instruction of a program and to identify data associated with the instruction. The execution module is operable to execute the instruction upon the data associated with the instruction. The MMW transceiver section is operable to wirelessly receive at least one of the instruction and the data associated with the instruction from memory.

Claims

1. A processing module comprises:

a fetch and decode module operable to fetch and decode an instruction of a program and to identify data associated with the instruction;

an instruction register module operable to store the instruction;

a data register module operable to store the data associated with the instruction;

an execution module operable to execute the instruction upon the data associated with the instruction; and

a millimeter wave (MMW) transceiver section operable to wirelessly receive at least one of the instruction and the data associated with the instruction from memory.

2. The processing module of claim 1 further comprises:

the instruction register module including at least one of an instruction cache and an instruction register; and

the data register module including at least one of data cache and a data register.

3. The processing module of claim 1, wherein the execution module comprises at least one of:

one or more arithmetic logic units;

one or more floating point units;

one or more branch prediction units; and

one or more single instruction multiple data (SIMD) units.

4. The processing module of claim 1, wherein the MMW transceiver section comprises:

a plurality of MMW transceivers.

5. The processing module of claim 4 further comprises:

a frame organization module coupled to the plurality of MMW transceivers, wherein the frame organization module functions to;

receive a fetch instruction command from the fetch and decode module;

receive a data retrieval message from the fetch and decode module; and

allocate at least some of the plurality of MMW transceivers for retrieving the instruction in accordance with the fetch instruction command and for retrieving the data associated with the instruction in accordance with the data retrieval message.

6. The processing module of claim 1 further comprises:

the fetch and decode module operable to fetch and decode a second instruction and to identify data associated with the second instruction;

a second instruction register module operable to store the second instruction;

a second data register module operable to store the data associated with the second instruction;

a second execution module operable to execute the second instruction upon the data associated with the second instruction; and

a second millimeter wave (MMW) transceiver section operable to wirelessly receive at least one of the second instruction and the data associated with the second instruction from the memory.

7. The processing module of claim 1 further comprises:

a write back module operable to write back an output of the execution module to at least one of the data register module and the memory.

8. A processing module comprises:

an execution unit operable to execute instruction upon data associated with the instruction to produce an output;

a control unit operable to;

generate an instruction fetch command to retrieve the instruction;

generate a data retrieval message regarding the data associated with the instruction; and

determine a write back command;

an instruction millimeter wave (MMW) transceiver operable to wirelessly retrieve the instruction from memory in accordance with the instruction fetch command;

a data MMW transceiver operable to wirelessly retrieve the data associated with the instruction from the memory in accordance with the data retrieval message; and

a write back MMW transceiver operable to wirelessly transmit the output to the memory in accordance with the write back command.

9. The processing module of claim 8 further comprises:

an instruction register module coupled to the control unit, the execution unit, and the instruction MMW transceiver, wherein the instruction register module temporarily stores one or more instructions, and wherein, when the one or more instructions does not include the instruction, the control unit generates the instruction fetch command.

10. The processing module of claim 8 further comprises:

a data register module coupled to the control unit, the execution unit, and the data MMW transceiver, wherein the data register module temporarily stores one or more data elements, and wherein, when the one or more data elements does not include the data associated with the instruction, the control unit generates the data retrieval message.

11. The processing module of claim 10 further comprises:

an output register module coupled to the control unit, the execution unit, and the write back MMW transceiver, wherein the output register module temporarily stores the output, and wherein, when the control unit determines that the output is to be written to the memory, the control unit generates the write back command and, when the control unit determines that the output is to be written to the data register, the control unit coordinates the writing of the output into the data register.

12. The processing module of claim 8 further comprises:

a second execution unit operable to execute a second instruction upon data associated with the second instruction to produce a second output;

the control unit operable to;

generate a second instruction fetch command to retrieve the second instruction;

generate a second data retrieval message regarding the data associated with the second instruction; and

determine a second write back command;

the instruction MMW transceiver operable to wirelessly retrieve the second instruction from the memory in accordance with the second instruction fetch command;

the data MMW transceiver operable to wirelessly retrieve the data associated with the second instruction from the memory in accordance with the second data retrieval message; and

the write back MMW transceiver operable to wirelessly transmit the second output to the memory in accordance with the second write back command.

13. The processing module of claim 8 further comprises:

a second execution unit operable to execute a second instruction upon data associated with the second instruction to produce a second output;

the control unit operable to;

generate a second instruction fetch command to retrieve the second instruction;

generate a second data retrieval message regarding the data associated with the second instruction; and

determine a second write back command;

a second instruction MMW transceiver operable to wirelessly retrieve the second instruction from the memory in accordance with the second instruction fetch command;

a second data MMW transceiver operable to wirelessly retrieve the data associated with the second instruction from the memory in accordance with the second data retrieval message; and

a second write back MMW transceiver operable to wirelessly transmit the second output to the memory in accordance with the second write back command.

14. The processing module of claim 8, wherein the control unit further functions to:

determine at least one channel of a plurality of channels for wirelessly retrieving the instruction by the instruction MMW transceiver;

determine at least one other channel of the plurality of channels for wirelessly retrieving that data associated with the instruction by the data MMW transceiver; and

determine at least one further channel of the plurality of channels for wirelessly transmitting the output by the write back MMW transceiver.

15. A processing module comprises:

an execution unit operable to execute instruction upon data associated with the instruction to produce an output;

a data register for temporarily storing the data associated with the instruction;

an output register for temporarily storing the output;

a data cache for storing a plurality of data elements;

an instruction register for temporarily storing the instruction;

an instruction cache for storing a plurality of instructions;

a control unit operable to;

generate an instruction fetch command to retrieve the instruction when the plurality of instructions does not include the instruction;

generate a data retrieval message regarding the data associated with the instruction when the plurality of data elements does not include the data associated with the instruction;

determine a first write back command when the output is to written to the data cache; and

determine a second write back command when the output is to be written to memory;

a millimeter wave (MMW) transceiver section operable to;

wirelessly convey the instruction from the memory to the instruction cache in accordance with the instruction fetch command;

wirelessly convey the data associated with the instruction from the memory to the data cache in accordance with the data retrieval message; and

wirelessly transmit the output to the memory in accordance with the second write back command.

16. The processing module of claim 15, wherein the MMW transceiver section comprises:

an instruction MMW transceiver operable to wirelessly convey the instruction from the memory to the instruction cache in accordance with the instruction fetch command; and

a data MMW transceiver operable to wirelessly convey the data associated with the instruction from the memory to the data cache in accordance with the data retrieval message.

17. The processing module of claim 16, wherein the memory comprises:

a second instruction cache;

a second instruction MMW transceiver coupled to the second instruction cache, wherein the instruction is conveyed between the second instruction cache and the instruction cache via the second instruction MMW transceiver and the instruction MMW transceiver;

a second data cache; and

a second data MMW transceiver coupled to the second data cache, wherein the data associated with the instruction is conveyed between the second data cache and the data cache via the second data MMW transceiver and the data MMW transceiver.

18. The processing module of claim 17, wherein the memory further comprises:

main memory; and

a main memory MMW transceiver coupled to the main memory, wherein the instruction is conveyed between the main memory and the second instruction cache via the main memory MMW transceiver and the second instruction MMW transceiver and wherein the data associated with the instruction is conveyed between the main memory and the second data cache via the main memory MMW transceiver and the second data MMW transceiver.

19. The processing module of claim 17 further comprises:

an integrated circuit that supports the execution unit, the data register, the output register, the data cache, the instruction register, the instruction cache, the control unit, the instruction MMW transceiver, the data MMW transceiver, the second instruction cache, the second instruction MMW transceiver, the second data cache, and the second data MMW transceiver.

20. The processing module of claim 17 further comprises:

a first integrated circuit that supports the execution unit, the data register, the output register, the data cache, the instruction register, the instruction cache, the control unit, the instruction MMW transceiver, and the data MMW transceiver; and

a second integrated circuit that supports the second instruction cache, the second instruction MMW transceiver, the second data cache, and the second data MMW transceiver.