DISTRIBUTED DIGITAL SIGNAL PROCESSOR

• US 20080320285A1
• Filed: 08/30/2008
• Published: 12/25/2008
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Markison, Timothy W.
• Granted Patent: US 8,280,303 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A distributed digital signal processor (DSP) includes instruction memory, data memory, a multiply-accumulate module, an instruction MMW transceiver, a data MMW transceiver, and a multiply-accumulate transceiver. The multiply-accumulate module performs a function upon first and second data elements in accordance with a command of an instruction. The instruction MMW transceiver transmits a MMW instruction signal that includes at least a portion of the instruction. The data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements. The multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal.

Claims

1. A distributed digital signal processor (DSP) comprises:

an instruction memory that stores a plurality of instructions;

a data memory that stores a plurality of data elements;

a multiply-accumulate module that performs a function upon first and second data elements of the plurality of data elements in accordance with a command of an instruction of the plurality of instructions to produce a resultant;

an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes at least a portion of the instruction;

a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements; and

a multiply-accumulate MMW transceiver coupled to the multiply-accumulate module, wherein the multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal.

2. The distributed DSP of claim 1, wherein the instruction MMW transceiver comprises:

a baseband processing module operable to;

retrieve the instruction from the instruction memory;

interpret the instruction to identify the function from a plurality of functions, an address of the first data element, and an address of the second data element;

convert the command corresponding to the function into a command symbol stream; and

convert the addresses of the first and second data elements into an addressed data symbol stream;

a MMW front end coupled to;

convert the command symbol stream into a MMW command signal; and

convert the addressed data symbol stream into a MMW addressed data signal, wherein the MMW instruction signal includes the MMW command signal and the MMW data signal.

3. The distributed DSP of claim 2, wherein the data MMW transceiver comprises:

a data MMW front end coupled to;

recover the addressed data symbol stream from the MMW data signal; and

convert a data symbol stream into the MMW data signal; and

a data baseband processing module coupled to;

recover the addresses of the first and second data elements from the addressed data symbol stream;

provide the addresses of the first and second data elements to the data memory;

receive the first and second data elements from the data memory; and

convert the first and second data elements into the data symbol stream.

4. The distributed DSP of claim 2, wherein the multiply-accumulate MMW transceiver comprises:

a multiply-accumulate MMW front-end coupled to;

recover a data symbol stream from the MWM data signal; and

recover the command symbol stream from the MMW command signal; and

a multiply-accumulate baseband processing module coupled to;

recover the first and second data elements from the data symbol stream; and

recover the command that corresponds to the function from the command symbol stream.

5. The distributed DSP of claim 1 further comprises:

a control unit operable to;

identify the instruction based on execution of an algorithm;

generate a retrieve instruction request for the instruction based on the execution of the algorithm;

identify the first and second data elements; and

generate a retrieve data request for the first and second data elements;

a control MMW transceiver coupled to;

convert the retrieve instruction request into a MMW retrieve instruction signal, wherein the instruction MMW transceiver transmits the MMW instruction signal in response to receiving the MMW retrieve instruction signal; and

convert the retrieve data request into a MMW data request signal, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW retrieve data signal.

6. The distributed DSP of claim 1, wherein the multiply-accumulate module comprises:

at least one multiplier; and

at least one of an arithmetic logic unit, an adder, and a bit manipulation module.

7. A distributed digital signal processor (DSP) comprises:

an instruction memory that stores a plurality of instructions;

a data memory that stores a plurality of data elements;

an arithmetic module that performs an arithmetic function upon a product of first and second data elements of the plurality of data elements in accordance with an instruction of the plurality of instructions to produce a resultant;

an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes the instruction;

a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver includes;

a baseband processing module coupled to;

receive the first and second data elements from the data memory;

convert the first data element into a first data symbol stream; and

convert the second data element into a second data symbol stream;

an up conversion mixing module coupled to;

mix the first data symbol stream, the second data symbol stream, and a transmit local oscillation in accordance with a multiply function of the instruction to produce a multiplied mixed signal that includes the product of first and second data elements;

a power amplifier module coupled to amplify the multiplied mixed signal to produce a MMW data product signal; and

an arithmetic MMW transceiver coupled to the arithmetic module, wherein the arithmetic MMW transceiver recovers the product of first and second data elements from the MMW data product signal and recovers the command corresponding to the arithmetic function from the MMW instruction signal.

8. The distributed DSP of claim 7, wherein the data MMW transceiver further comprises:

a low noise amplifier coupled to amplify the MMW instruction signal to produce an amplified MMW instruction signal;

a down conversion mixing module coupled to convert the amplified MMW instruction signal into an instruction symbol stream in accordance with a local oscillation;

the baseband processing module coupled to;

recover the instruction from the instruction symbol stream;

interpret the instruction to identify addresses of the first and second data elements and a multiply function;

provide the addresses of the first and second data elements to the data memory;

receive the first and second data elements from the data memory;

convert the first data element into a first data symbol stream; and

convert the second data element into a second data symbol stream;

9. The distributed DSP of claim 7, wherein the up conversion mixing module comprises:

a first multiplier coupled to multiply the first data symbol stream, the second data symbol stream, and the transmit local oscillation to produce an intermediate product; and

a filter module coupled to filter the intermediate product to the multiplied mixed signal.

10. The distributed DSP of claim 7, wherein the up conversion mixing module comprises:

a first multiplier;

a second multiplier;

a first filter;

a second filter;

a second power amplifier module; and

a multiplexer coupled to the first and second multipliers, wherein;

in accordance with the multiply function of the instruction;

the multiplexer provides the second data symbol stream to the first multiplier;

the first multiplier multiplies the first data symbol stream, the second data symbol stream, and the transmit local oscillation to produce an intermediate product; and

the first filter module coupled to filter the intermediate product to produce the multiplied mixed signal; and

in accordance with a data request of the instruction;

the multiplexer provides the second data symbol stream to the second multiplier;

the first multiplier multiplies the first data symbol stream and the transmit local oscillation to produce a first mixed signal; and

the first filter module coupled to filter the first mixed signal to produce a first MMW data signal;

the second multiplier multiplies the second data symbol stream and the transmit local oscillation to produce a second mixed signal;

the second filter module coupled to filter the second mixed signal to produce a second MMW data signal;

the second power amplifier amplifies the second MMW data signal.

11. The distributed DSP of claim 7, wherein the instruction MMW transceiver comprises:

a baseband processing module operable to;

retrieve the instruction from the instruction memory;

interpret the instruction to identify a multiply command corresponding to the multiply function of the instruction, an arithmetic command, an address of the first data element, and an address of the second data element;

convert the arithmetic command into a command symbol stream; and

convert the multiply command and the addresses of the first and second data elements into an address and multiply command symbol stream;

a MMW front end coupled to;

convert the command symbol stream into a MMW arithmetic command signal; and

convert the address and multiply command symbol stream into a MMW address and command signal, wherein the MMW instruction signal includes the MMW arithmetic command signal and the MMW address and multiply command signal.

12. The distributed DSP of claim 7 further comprises:

a control unit operable to;

identify the instruction and the first and second data elements based on execution of an algorithm; and

generate a retrieve instruction request for the instruction based on the execution of the algorithm;

a control MMW transceiver coupled to;

convert the retrieve instruction request into a MMW retrieve instruction signal, wherein the instruction MMW transceiver transmits the MMW instruction signal in response to receiving the MMW retrieve instruction signal.

13. A distributed digital signal processor (DSP) comprises:

an instruction memory that stores a plurality of instructions;

a data memory that stores a plurality of data elements;

an arithmetic module that performs an arithmetic function upon a product of first and second data elements of the plurality of data elements in accordance with an instruction of the plurality of instructions to produce a resultant;

an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes the instruction;

a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver transmits a first MMW data signal and second MMW data signal in response to receiving the MMW instruction signal, wherein the first MMW data signal includes the first data element and the second MMW data signal includes the second data element; and

an arithmetic MMW transceiver coupled to the arithmetic module, wherein the arithmetic MMW transceiver includes;

a low noise amplifier section coupled to;

amplify the MMS instruction signal to produce an amplified MMW instruction signal;

amplify the first MMW data signal to produce a first amplified MMW data signal; and

amplify the second MMW data signal to produce a second amplified MMW data signal;

a down conversion section coupled to;

convert the amplified MMW instruction signal into an instruction symbol stream; and

mix the first amplified MMW data signal, the second amplified MMW data signal, and a receive local oscillation to produce a mixed down converted signal in accordance with a multiply command; and

a baseband processing module coupled to;

recover the command and the multiply command from the instruction symbol stream;

convert the mixed down converted signal into the product of first and second data elements; and

provide the product of the first and second data elements to the arithmetic module.

14. The distributed DSP of claim 13, wherein the low noise amplifier section comprises:

a first low noise amplifier coupled to amplify the MMS instruction signal to produce the amplified MMW instruction signal;

a second low noise amplifier coupled to amplify the first MMW data signal to produce the first amplified MMW data signal; and

a third low noise amplifier coupled to amplify the second MMW data signal to produce the second amplified MMW data signal.

15. The distributed DSP of claim 14, wherein the down conversion section comprises:

a first mixing module coupled to mix the amplified MMW instruction signal with the receive local oscillation to produce a down converted instruction signal;

a first filter module coupled to filter the down converted instruction signal to produce the instruction symbol stream;

a second mixing module coupled to mix the first amplified MMW data signal, the second amplified MMW data signal, and the receive local oscillation in accordance with the multiple command to produce a second down converted signal; and

a second filter module coupled to filter the second down converted signal to produce the mixed down converted signal.

16. The distributed DSP of claim 15, wherein the down conversion section further comprises:

a multiplexer coupled to provide the second amplified MMW data signal to the second mixing module in accordance with the multiply command and to provide the second amplified MMW data signal to a third mixing module in accordance with a second multiply command;

the third mixing module coupled to mix the second amplified MMW data signal and the receive local oscillation to produce a third down converted signal, wherein the second mixing module mixes the first amplified MMW data signal and the receive local oscillation to produce a fourth down converted signal and the second filter module filters the fourth down converted signal to produce a filtered fourth down converted signal;

a third filter module coupled to filter the third down converted signal to produce a filtered third down converted signal;

a multiplying module coupled to multiply the filtered third and fourth down converted signals to produce the mixed down converted signal.

17. The distributed DSP of claim 13, wherein the instruction MMW transceiver comprises:

a baseband processing module operable to;

retrieve the instruction from the instruction memory;

interpret the instruction to identify a command corresponding to the multiply function of the instruction, an address of the first data element, and an address of the second data element;

convert the command corresponding to the multiply function into a command symbol stream;

convert the addresses of the first data element into a first addressed data symbol stream; and

convert the addresses of the second data element into a second addressed data symbol stream;

a MMW front end coupled to;

convert the command symbol stream into a MMW command signal; and

convert the first addressed data symbol stream into a first MMW addressed data signal; and

convert the second addressed data symbol stream into a second MMW addressed data signal, wherein the MMW instruction signal includes the MMW command signal, the first MMW addressed data signal, and the second MMW addressed data signal.

18. The distributed DSP of claim 13 further comprises:

a control unit operable to;

identify the instruction and the first and second data elements based on execution of an algorithm; and

generate a retrieve instruction request for the instruction based on the execution of the algorithm;

a control MMW transceiver coupled to;

convert the retrieve instruction request into a MMW retrieve instruction signal, wherein the instruction MMW transceiver transmits the MMW instruction signal in response to receiving the MMW retrieve instruction signal.

19. A digital signal processing (DSP) module comprises:

an arithmetic module operable to execute an instruction upon data associated with the instruction to produce a resultant;

a control module wireless coupled to at least one of a data memory, an instruction memory, and the arithmetic module, wherein the control module coordinates retrieval of the instruction from a plurality of instructions stored in the instruction memory and retrieval of the data of a plurality of data elements stored in the data memory; and

a first millimeter wave (MMW) transceiver section operable to support the wireless coupling of the control module to the least one of the data memory, the instruction memory, and the arithmetic module.

20. The DSP module of claim 19 further comprises:

a second MMW transceiver section coupled to the arithmetic unit to support wireless communication between the control module and the arithmetic unit;

a first integrated circuit that supports the control module, the first MMW transceiver section and the instruction memory; and

a second integrated circuit that supports the arithmetic unit, the second MMW transceiver and the data memory.

21. The DSP module of claim 19 further comprises:

a second MMW transceiver section coupled to memory, wherein the first MMW transceiver provides a wireless link between the control module and the memory via the second MMW transceiver section, and wherein the memory includes the data memory and the instruction memory;

a first integrated circuit that supports the first MWM transceiver section, the arithmetic unit, and the control module; and

a second integrated circuit that supports the second MMW transceiver section and the memory.

22. The DSP module of claim 19 further comprises:

a second MMW transceiver section coupled to the data memory, wherein the first MMW transceiver provides a data wireless link between the control module and the data memory via the second MMW transceiver section;

a third MMW transceiver section coupled to the instruction memory, wherein the first MMW transceiver provides an instruction wireless link between the control module and the instruction memory via the third MMW transceiver section;

a first integrated circuit that supports the first MWM transceiver section, the arithmetic unit, and the control module;

a second integrated circuit that supports the second MMW transceiver section and the data memory; and

a third integrated circuit that supports the third MMW transceiver section and the instruction memory.