CONFIGURABLE PROCESSING CORE

• US 20080320293A1
• Filed: 08/30/2008
• Published: 12/25/2008
• Est. Priority Date: 01/31/2007
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Markison, Timothy W.
• Application Number:
  US12/202,259
• Publication Number:
  US 20080320293A1
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A configurable processing core includes a configuration module and a plurality of functional blocks, each including a millimeter wave (MMW) transceiver. The configuration module is operable to determine configuration of at least some of the plurality of functional blocks based on at least one instruction of an algorithm, generate a configuration signal in accordance with the determined configuration, and transmit the configuration signal to the at least some of the plurality of functional blocks via the MMW transceivers. The at least some of the plurality of functional blocks are operable to configure in accordance with the configuration signal to support execution of the at least one instruction.

Claims

1. A configurable processing core comprises:

a configuration module that includes a configuration millimeter wave (MMW) transceiver; and

a plurality of functional blocks, wherein each of the plurality of functional blocks includes a functional MMW transceiver and wherein;

the configuration module is operable to;

determine configuration of at least some of the plurality of functional blocks based on at least one instruction of an algorithm;

generate a configuration signal in accordance with the determined configuration; and

transmit the configuration signal to the at least some of the plurality of functional blocks via the configuration MMW transceiver and the functional MMW transceivers associated with the at least some of the plurality of functional blocks; and

wherein;

the at least some of the plurality of functional blocks are operable to configure in accordance with the configuration signal to support execution of the at least one instruction.

2. The configurable processing core of claim 1, wherein the configuration module is further operable to determine the configuration of at least some of the plurality of functional blocks by:

interpreting the at least one instruction to identify the at least some of the plurality of functional blocks;

determining wireless communication links between the at least some of the plurality of functional blocks;

determining data rate requirements for each of the wireless communication links; and

allocating, when available, wireless communication resources to the wireless communication links based on the data rate requirements.

3. The configurable processing core of claim 2, wherein the configuration module is further operable to allocate, when available, the wireless communication resources by at least one of:

determining whether one or more of the wireless communication links requires one or more temporary dedicated channels of a plurality of channels, wherein the plurality of channels spans one or more frequency bands;

determining whether another one or more of the wireless communication links requires a temporary shared channel of the plurality of channels;

when the one or more of the wireless communication links requires the one or more temporary dedicated channels, allocating one or more of the plurality of channels for each wireless communication link requiring the one or more temporary dedicated channels; and

when the another one or more of the wireless communication links requires the temporary shared channel, allocating division multiple access slots of the temporary shared channel to the another one or more of the wireless communication links.

4. The configurable processing core of claim 1, wherein the plurality of functional blocks comprises two or more of:

a floating point adder;

a floating point multiplier;

a register;

an integer adder;

an integer multiplier;

a shift register;

an accumulator;

a logic unit; and

a delay.

5. The configurable processing core of claim 4, wherein the configuration module is further operable to:

generate the configuration signal to configure one or more of the floating point adder, the floating point multiplier, the register, the integer adder, the integer multiplier, the shift register, the accumulator, the logic unit, and the delay into a single microprocessing core.

6. The configurable processing core of claim 4, wherein the configuration module is further operable to:

generate the configuration signal to configure one or more of the floating point adder, the floating point multiplier, the register, the integer adder, the integer multiplier, the shift register, the accumulator, the logic unit, and the delay into a multiple parallel processing core.

7. The configurable processing core of claim 4, wherein the configuration module is further operable to:

generate the configuration signal to configure one or more of the floating point adder, the floating point multiplier, the register, the integer adder, the integer multiplier, the shift register, the accumulator, the logic unit, and the delay into a single digital signal processor core.

8. The configurable processing core of claim 4, wherein the configuration module is further operable to:

generate the configuration signal to configure one or more of the floating point adder, the floating point multiplier, the register, the integer adder, the integer multiplier, the shift register, the accumulator, the logic unit, and the delay into a multiple parallel digital signal processor core.

9. The configurable processing core of claim 4, wherein the configuration module is further operable to:

generate the configuration signal to configure one or more of the floating point adder, the floating point multiplier, the register, the integer adder, the integer multiplier, the shift register, the accumulator, the logic unit, and the delay into a parallel processor core and digital signal processor core.

10. The configurable processing core of claim 1 further comprises:

the MMW transceiver transmits the configuration signal to the function MMW transceivers of the plurality of functional blocks via a dedicate control channel.

11. A configurable processing core comprises:

a first functional block having a first millimeter wave (MMW) transceiver;

a second functional block having a second MMW transceiver; and

a third functional block having a third MMW transceiver, wherein the first, second, and third functional blocks wireless communicate with at least one other of the first, second, and third functional blocks via the first, second, or third MMW transceivers to execute at least one instruction of an algorithm.

12. The configurable processing core of claim 11 further comprises:

a configuration module that includes a configuration unit and a configuration MMW transceiver, wherein the configuration module is operable to;

interpret the at least one instruction;

determine configuration of the first, second, and third functional blocks based on the interpreting;

generate a configuration signal in accordance with the configuration of the first, second, and third functional blocks; and

transmit, via the configuration MMW transceiver, the configuration signal to the first, second, and third MMW transceivers.

13. The configurable processing core of claim 12 further comprises:

a plurality of functional blocks, wherein each of the plurality of functional blocks includes a functional circuit and a MMW transceiver;

wherein the configuration module generates the configuration signal to configure at least some of the plurality of functional blocks and the first, second, and third functional blocks.

14. The configurable processing core of claim 12, wherein the plurality of functional blocks, the first, second, and third functional blocks comprises at least some of:

a floating point adder;

a floating point multiplier;

a register;

an integer adder;

an integer multiplier;

a shift register;

an accumulator;

a logic unit; and

a delay.

15. A configurable processing core comprises:

a plurality of register modules, wherein each of the plurality of register modules includes a register and a register millimeter wave (MMW) transceiver;

a plurality of adder modules, wherein each of the plurality of adder modules includes an adder and an adder MMW transceiver;

a plurality of multiplier modules, wherein each of the plurality of multiplier modules includes a multiplier and a multiplier MMW transceiver;

a plurality of shift register modules, wherein each of the plurality of shift register modules includes a shift register and a shift register MMW transceiver; and

a configuration module that includes a configuration MMW transceiver, wherein the configuration module is operable to generate a configuration signal and transmit the configuration signal via the configuration MMW transceiver, wherein at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers are configured in accordance with the configuration signal to execute an instruction of an algorithm.

16. The configurable processing core of claim 15 further comprises:

the plurality of multiplier modules including a plurality of floating point multipliers and a plurality of integer multipliers; and

the plurality of adder modules including a plurality of floating point adders and a plurality of integer adders.

17. The configurable processing core of claim 15 further comprises at least one of:

a plurality of accumulator modules, wherein each of the plurality of accumulator modules includes an accumulator and an accumulator MMW transceiver; and

a plurality of delay modules, wherein each of the plurality of delay modules includes a delay and a delay MMW transceiver.

18. The configurable processing core of claim 15, wherein the configuration module is further operable to:

generate the configuration signal to configure the at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers into a single microprocessing core.

19. The configurable processing core of claim 15, wherein the configuration module is further operable to:

generate the configuration signal to configure the at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers into a multiple parallel processing core.

20. The configurable processing core of claim 15, wherein the configuration module is further operable to:

generate the configuration signal to configure the at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers into a single digital signal processor core.

21. The configurable processing core of claim 15, wherein the configuration module is further operable to:

generate the configuration signal to configure the at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers into a multiple parallel digital signal processor core.

22. The configurable processing core of claim 15, wherein the configuration module is further operable to:

generate the configuration signal to configure the at least some of the plurality of register modules, the plurality of adder modules, the plurality of multiplier modules, and the plurality of shift registers a parallel processor core and digital signal processor core.