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FEATURE EXTRACTION THAT SUPPORTS PROGRESSIVELY REFINED SEARCH AND CLASSIFICATION OF PATTERNS IN A SEMICONDUCTOR LAYOUT

  • US 20080320421A1
  • Filed: 06/20/2007
  • Published: 12/25/2008
  • Est. Priority Date: 06/20/2007
  • Status: Abandoned Application
First Claim
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1. A method of identifying patterns in a semiconductor layout, the method comprising:

  • specifying a target region by indicating polygonal regions on a mask layer;

    generating a target vector using a two dimensional (2D) low discrepancy sequence;

    identifying layout regions in a design layout;

    generating a feature vector for a layout region;

    comparing a subset of sequence derived feature values in the target vector with sequence derived feature values in a search region feature vector as an initial filter;

    determining that the layout region does not contain a match if a comparison of the subset of sequence derived feature values in the target vector with corresponding values in the search region feature vector falls below a threshold; and

    outputting search results.

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